Multiphase PWM Circuit Using Fractional Clock Intervals

The patent segments the clock period into multiple phases (first clock phase and second clock phase) that are phase-shifted relative to each other. The PWM signal generation is divided into multiple sub-intervals, each controlled by a different clock phase. This segmentation allows the system to achieve high resolution PWM control without requiring a single high-frequency clock, thereby reducing switching losses while maintaining measurement precision.

The patent introduces a temporal dimension by using multiple phase-shifted clock phases instead of relying solely on a single clock frequency. By distributing the PWM generation across multiple phase intervals, the system achieves higher resolution in the time domain without increasing the overall clock frequency or complicating the digital implementation. This dimensional approach to time management resolves the contradiction between simplicity and precision.

The patent merges the functionality of multiple clock phases into a unified PWM generation process. The first and second clock phases are combined to control different sub-intervals of the PWM period, with their outputs integrated to produce the final high-resolution PWM signal. This merging approach achieves high duty cycle control precision while avoiding the need for separate complex control circuits for each phase, thereby managing device complexity effectively.