Fractional Clock Ramp Control With Coarse-Fine Frequency Steps
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Solution Overview
Problem
Existing clock signal generators face issues with unequal duration frequency change steps and low resolution in achieving target frequencies, leading to voltage droops and potential malfunctions in integrated circuits, due to unsynchronized counters and inefficient divider ratio selection algorithms.
Innovation Solution
A fractional clock divider with synchronized counters and a frequency ramp control circuit that generates equal duration frequency change steps and selects divider ratios for coarse and fine frequency changes to achieve fast and high-resolution frequency ramps, using a combination of counters and an M/N determining device to synchronize the duration of each step and select appropriate divider ratios.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the frequency of the output clock signal is changed in large positive steps, then the frequency ramp speed is improved, but the voltage droop increases causing malfunction or adverse effects in the core operation
Solution Approach 1:
The frequency change from current frequency to target frequency is divided into multiple discrete steps rather than a single large change. The frequency ramp control circuit generates a sequence of intermediate frequencies that incrementally approach the target frequency, with each step causing only a small current surge and corresponding small voltage droop that allows the power supply to recover.
Solution Approach 2:
The frequency change process is made dynamic and adaptive through the use of synchronized counters and a frequency ramp control circuit that automatically adjusts the timing and magnitude of frequency steps. The system dynamically determines the number of steps and their duration based on the frequency difference between current and target frequencies, optimizing both speed and voltage stability.
2Productivity
If the frequency change steps have unequal duration, then the frequency ramp can be completed faster, but the voltage droops occur at irregular intervals causing potential malfunctions
Solution Approach 1:
The frequency change steps are made periodic and regular in duration through the use of synchronized counters. The first counter generates indices at regular intervals, and the second counter generates control signals with equal duration steps, creating a periodic frequency ramp pattern that ensures voltage droops occur at regular, predictable intervals, allowing the power supply to recover between each droop event.
3Device complexity
If the counters are not synchronized, then the circuit complexity is reduced, but the frequency change steps have unequal duration reducing the resolution in achieving target frequency
Solution Approach 1:
The synchronization of the first and second counters is achieved by merging their clock sources to the same input clock signal. This combining of timing references ensures that both counters operate at the same frequency and phase relationship, producing equal duration frequency change steps and enabling high-resolution accurate achievement of target frequency without requiring complex independent timing circuits.
Data Source
AI summary
A clock signal generator including a fractional clock divider and a frequency ramp control circuit. The fractional clock divider is configured to generate an output clock signal with a frequency being a divider ratio multiplied by a frequency of an input clock signal. The frequency ramp control circuit is configured to provide the fractional clock divider a set of divider ratios so that the frequency of the output clock signal is ramped in steps from a current frequency to a target frequency. The frequency ramp control circuit is configured to produce frequency change steps each having substantially the same duration. The frequency ramp control circuit is also configured to provide the set of divider ratios such as a first portion of the frequency ramp is performed using coarse frequency changes and a second portion of the ramp is performed using at least one fine frequency change.