Fractional Multi-Core Virtualization for Power Efficiency
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Solution Overview
Problem
Multi-core processors experience low utilization and inefficiency due to design inflexibility, leading to wasted power and challenges in optimizing software performance as the number of cores increases, particularly in symmetric MCPs where only a portion of processing elements are utilized, resulting in high power consumption and inefficiency.
Innovation Solution
The fractionalization of multi-core systems and memory systems using virtualization techniques, where a group of cores or memory modules are configured as fractional cores or caches, allowing for dynamic reconfiguration and efficient utilization of resources, such as fractional address translation tables and fractional cache controllers, to improve power efficiency and flexibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If multi-core processors are designed with symmetric processing elements, then processing capability is improved, but utilization efficiency deteriorates due to inflexible design preventing optimal resource allocation
Solution Approach 1:
The patent segments processing elements into heterogeneous groups with different capabilities (e.g., high-performance cores and power-efficient cores). This segmentation allows the system to allocate specific processing elements to specific tasks based on their individual characteristics, improving overall utilization efficiency while maintaining high processing capability through the combined strengths of different core types.
Solution Approach 2:
The patent implements dynamic reconfiguration capabilities that allow the processing elements to be dynamically allocated and reassigned based on workload requirements. This dynamic adjustment enables the system to optimize utilization efficiency by activating only the processing elements needed for current tasks, while maintaining the ability to handle diverse workloads through the heterogeneous architecture.
2Power
If more processing elements are added to multi-core processors, then processing capability is improved, but power consumption increases due to continuous operation of all cores
Solution Approach 1:
The patent divides processing elements into segments with different power characteristics. Power-efficient processing elements can be activated only when needed for specific tasks, while high-performance cores remain in lower-power states. This segmentation enables the system to achieve high processing capability when required while minimizing power consumption during idle or low-demand periods.
Solution Approach 2:
The patent applies partial action by activating only the necessary portion of processing elements for current workloads rather than all cores. This allows the system to provide sufficient processing capability for current tasks while avoiding the power consumption penalty of keeping all processing elements in high-performance states, effectively using partial resources when full resources are not needed.
3Speed
If processing elements are kept in high-performance state continuously, then response time is improved, but power consumption increases
Solution Approach 1:
The patent implements dynamic state management where processing elements can be transitioned between different performance states based on workload predictions and requirements. This allows the system to maintain low response times for critical tasks by keeping essential cores in appropriate states while powering down or clocking down less-needed processing elements, achieving a balance between response time and power consumption.
Solution Approach 2:
The patent applies preliminary action by pre-warming critical processing elements or keeping them in low-power ready states based on predicted workload patterns. This ensures that when tasks need to execute, the necessary processing elements are already in or near optimal states, maintaining acceptable response times while reducing the duration of high-power consumption compared to continuous high-performance operation.
Data Source
AI summary
A system, method, and computer program product are provided for a processing unit including a plurality of processing cores including a first processing core and a second processing core. In use, the processing unit is configured such that a virtual processing core is capable of being virtualized utilizing at least a portion of the first processing core and at least a portion of the second processing core. Such virtualization is further carried out such that at least one of the at least portion of the first processing core or the at least portion of the second processing core includes only a part thereof.