Fractional Data Packing Circuit for Scan Test Time Reduction
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Solution Overview
Problem
Current scan compression techniques face challenges in reducing test data volume and time, especially in low-cost testers and pin-limited devices, where the number of scan inputs and outputs are limited, leading to increased test timing and overhead due to serializer approaches that do not support non-integer multiples of pins.
Innovation Solution
A circuit and method that utilize input and output converters to generate pseudo scan inputs and outputs, allowing for fractional data packing and flexible frequency ratios, enabling efficient testing across devices with varying pin counts without requiring integer multiples of pins, thus reducing test timing and eliminating don't care inputs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If scan compression architecture uses more scan inputs and scan outputs, then test time is reduced, but device complexity increases due to additional shift registers and serializer overhead
Solution Approach 1:
The patent divides the scan input and scan output signals into multiple segments processed through separate decompressor and compressor units. By segmenting the scan data flow, the system achieves higher effective scan input/output counts without requiring a single complex serializer, thereby reducing test time while avoiding excessive device complexity
Solution Approach 2:
The decompressor and compressor units are designed to handle multiple scan chains simultaneously with flexible configuration. These universal units can adapt to different numbers of scan inputs and outputs, eliminating the need for dedicated serializer hardware for each configuration, thus reducing test time without proportionally increasing device complexity
2Adaptability or versatility
If serializer approach is used for pin-limited devices, then compatibility is improved, but test timing increases due to reduced data shifting frequency
Solution Approach 1:
The patent introduces decompressor and compressor units as intermediary components between the scan inputs/outputs and the scan chains. These intermediaries efficiently pack and unpack scan data, enabling pin-limited devices to achieve higher effective scan rates without the frequency reduction penalty of traditional serializers, thus improving compatibility while reducing test timing
Solution Approach 2:
The system dynamically adjusts the number of scan inputs and outputs supported by reconfiguring the decompressor and compressor units. This parameter flexibility allows pin-limited devices to operate at optimal test frequencies without being constrained by fixed serializer configurations, thereby improving compatibility while minimizing test timing
3Loss of time
If number of scan inputs is increased from 8 to 9, then test time is reduced by 50%, but VLCT compatibility is lost as VLCT only supports maximum 8 scan inputs and 8 scan outputs
Solution Approach 1:
The patent implements a nested structure where multiple scan inputs are logically grouped and processed through the decompressor unit. The decompressor internally manages the expansion of N scan inputs into M pseudo scan inputs, allowing the system to achieve 9-way parallelism while physically interfacing with VLCT's 8-input constraint, thus reducing test time while maintaining VLCT compatibility
Solution Approach 2:
The system transitions from a single-dimensional constraint (8 scan inputs) to a multi-dimensional solution by adding temporal dimension through pipelined decompression. Data from multiple scan inputs is processed in overlapping time windows, effectively achieving 9 simultaneous scan inputs through time-multiplexed decompression while maintaining compatibility with VLCT's 8-input interface
Data Source
AI summary
An embodiment provides a circuit for testing an integrated circuit. The circuit includes an input converter that receives N scan inputs and generates M pseudo scan inputs, where M and N are integers. A scan compression architecture is coupled to the input converter and generates P pseudo scan outputs in response to the M pseudo scan inputs. An output converter is coupled to the scan compression architecture and generates Q scan outputs in response to the P pseudo scan outputs, wherein P and Q are integers. The input converter receives the N scan inputs at a first frequency and generates the M pseudo scan inputs at a second frequency and the output converter receives the P pseudo scan outputs at the second frequency and generates the Q scan outputs at the first frequency.