Fractional Period Delay Generation With Sub-Sampling Feedback
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing delay generation systems face challenges in maintaining accuracy and resolution due to process variability and temperature changes, particularly in generating precise fractional periodic delays without requiring separate calibration phases, which can lead to increased errors and hardware overhead.
Innovation Solution
A system comprising a controllable delay line block, a sampling block, and a delay measurement unit that uses sub-sampling to generate sub-sampled signals, allowing for closed-loop feedback to adjust tap values and achieve accurate fractional period delays without calibration, thereby improving accuracy and reducing area overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If locking based methods with DLL and controllable delay buffers are used, then delay generation is achieved, but accuracy and resolution deteriorate due to process variability and coarse minimum delay
Solution Approach 1:
The patent implements a feedback mechanism where the generated delay signal is fed back to a phase detector that compares it with a reference signal. The phase detector output adjusts the delay buffers to maintain the desired phase relationship, continuously compensating for process variability and drift, thereby achieving high accuracy without requiring precise manufacturing tolerances
Solution Approach 2:
The patent uses dynamic delay buffers whose delay values can be continuously adjusted based on feedback from the phase detector. This dynamic adjustment allows the system to adapt to process variations and maintain accurate fractional period delays despite manufacturing imprecisions in the fixed delay stages
2Measurement precision
If calibration based methods are used, then accuracy is improved, but separate calibration phase is required causing interruption and increased hardware overhead
Solution Approach 1:
The patent maintains continuous operation by implementing feedback-based error correction during normal delay generation. The phase detector continuously monitors the phase difference and adjusts the delay buffers in real-time, eliminating the need for separate calibration phases and ensuring uninterrupted signal availability
Solution Approach 2:
The feedback mechanism serves multiple functions: it enables accurate fractional period delay generation, compensates for process variability, eliminates calibration requirements, and provides continuous error correction. This multi-functional approach reduces hardware overhead by integrating calibration capabilities into the normal operation pathway
Data Source
AI summary
Embodiments of the disclosure relate to an all-digital technique for generating an accurate delay irrespective of the inaccuracies of a controllable delay line. A sub-sampling technique based delay measurement unit capable of measuring delays accurately for the full period range is used as the feedback element to build accurate fractional period delays based on input digital control bits. The delay generation system periodically measures and corrects the error and maintains it at the minimum value without requiring any special calibration phase. A significant improvement in accuracy is obtained for a commercial programmable delay generator chip. The time-precision trade-off feature of the delay measurement unit is utilized to reduce the locking time. Loop dynamics are adjusted to stabilize the delay after the minimum error is achieved, thus avoiding additional jitter.