Fractional-Delay TDC Circuit for Finer PLL Time Resolution
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Solution Overview
Problem
Time-to-digital converters (TDCs) in phase-locked loops face challenges in achieving fine time resolution due to dependence on propagation speed changes of delay line inverters, leading to increased phase noise in PLLs.
Innovation Solution
A novel TDC design incorporates a fractional-delay element circuit, a first and second delay line timestamp circuit, and a programmable delay element to generate a high-resolution timestamp by time-shifting signals by half an inverter propagation delay, using a feedback loop to control the programmable delay element and maintain the desired time-shift relationship between signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a conventional delay line TDC is used, then the circuit structure is simple, but the time resolution is coarse and dependent on inverter propagation speed variations
Solution Approach 1:
The patent divides the measurement function into two independent segments: a coarse measurement from the first DLTC using the original DCO_OUT signal, and a fine measurement from the second DLTC using the time-shifted DCO_OUT_B signal. This segmentation allows each segment to be optimized independently, achieving fine time resolution without proportionally increasing overall complexity.
Solution Approach 2:
The patent creates a copy of the DCO_OUT signal (DCO_OUT_B) and applies a controlled time shift to it. This copied and shifted signal is then fed to the second DLTC, allowing the system to measure fractional delay portions without requiring a complete redesign of the TDC architecture.
2Measurement precision
If the inverter propagation delay is reduced to improve time resolution, then the time measurement becomes more precise, but the timestamp becomes more sensitive to propagation speed changes
Solution Approach 1:
The patent implements a feedback mechanism where the measured propagation delay is used to dynamically adjust the time shift applied to DCO_OUT_B. This feedback loop compensates for propagation speed variations, maintaining the stability of the timestamp while preserving fine time resolution.
Solution Approach 2:
The patent changes the time shift parameter dynamically based on measured propagation delay. By adjusting this parameter in response to propagation speed changes, the system maintains measurement precision without becoming sensitive to propagation variations.
3Measurement precision
If a single DLTC is used, then the device complexity is low, but the time resolution is limited by the inverter propagation delay
Solution Approach 1:
The patent adds a temporal dimension to the measurement by introducing a controlled time shift between the two DLTC inputs. This transforms the measurement from a single-dimensional coarse measurement into a two-dimensional measurement system that captures both integer and fractional delay components.
Data Source
AI summary
A time-to-digital converter (TDC) can have a resolution that is finer than the propagation delay of an inverter. In one example, a fractional-delay element circuit receives a TDC input signal and generates therefrom a second signal that is a time-shifted facsimile of a first signal. The first signal is supplied to a first delay line timestamp circuit (DLTC) and the second signal is supplied to a second DLTC. The first DLTC generates a first timestamp indicative of a time between an edge of a reference input signal to the TDC and an edge of the first signal. The second DLTC generates a second timestamp indicative of a time between the edge of the reference input signal and an edge of the second signal. The first and second timestamps are combined and together constitute a high-resolution overall TDC timestamp that has a finer resolution than either the first or second timestamps.