Programmable Delay Circuit With Fractional Timing Resolution
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Solution Overview
Problem
Synchronous circuits, such as flip-flops and latches, often experience misalignment of data and clock signals due to different propagation delays, which can limit their operating speed and timing margins.
Innovation Solution
A programmable delay circuit that provides integer and fractional time resolution, allowing for precise alignment of clock and data signals by combining N-stage full delay, half delay, quarter delay circuits, and single-ended-to-differential conversion, enabling flexible delay settings through control signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If integer delay only is used, then device complexity is reduced, but timing precision is insufficient
Solution Approach 1:
The delay circuit is segmented into multiple independent delay stages (first delay circuit, second delay circuit, third delay circuit) that can be selectively activated. Each stage provides a specific delay increment (T_unit, T_unit/2, T_unit/4), allowing fine-grained control of total delay time while keeping each individual stage relatively simple.
Solution Approach 2:
The delay circuit transitions from a static integer-delay-only design to a dynamic programmable design where the total delay can be adjusted in real-time by controlling which delay stages are activated. Control signals dynamically enable or disable specific delay circuits to achieve precise timing alignment.
2Reliability
If signal alignment is not achieved, then timing margins are reduced, but adding delay circuits increases device complexity
Solution Approach 1:
The delay circuit automatically adjusts its own delay characteristics through control signals to achieve signal alignment. The programmable nature allows the circuit to self-tune the delay amount based on the specific timing requirements of the connected synchronous circuit, eliminating the need for external manual adjustment or complex external alignment mechanisms.
3Measurement precision
If fractional delay is added to integer delay, then delay precision is improved, but device complexity increases
Solution Approach 1:
The patent merges multiple delay circuits with different delay characteristics (integer delay, half-integer delay, quarter-integer delay) into a unified programmable delay system. By combining these delay stages and controlling them through coordinated control signals, the system achieves fine-resolution fractional delay control while sharing common control logic and signal paths.
Data Source
AI summary
A programmable delay circuit capable of providing a delay with integer and fractional time resolution is described. In one exemplary design, an apparatus includes first and second delay circuits. The first delay circuit provides a first delay of an integer number of time units. The second delay circuit couples to the first delay circuit and provides a second delay of a fraction of one time unit. The first delay circuit may include multiple unit delay cells coupled in series. Each unit delay cell may provide a delay of one time unit when enabled. The second delay circuit may have first and second paths. The first path may provide a shorter delay when selected, and the second path may provide a longer delay when selected. The second path may be coupled to at least one dummy logic gate that provides extra loading to obtain the longer delay for the second path.