Shifted Fractional Divider for PLL Boundary Noise Suppression
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Solution Overview
Problem
Conventional fractional divider PLLs face issues with generating accurate fractional dividing values for frequency-modulated signals, leading to undesirable artifacts like spurious energy and noise due to concurrent changes in integer and fractional components, caused by differences in path delays.
Innovation Solution
The implementation of a shifting fractional divider system that selectively shifts and scales the fractional component of the dividing value using a shift value, avoiding concurrent changes in integer and fractional components by applying a shift to the fractional component, thereby maintaining accurate generation of fractional dividing values even when the signal crosses an N boundary.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional fractional divider PLL alternates among multiple integer dividing values over time to achieve fractional division, then the PLL can output a fractional multiple of the reference frequency, but undesirable artifacts like spurious energy and noise are produced when the signal crosses N boundaries due to concurrent changes in integer and fractional components
Solution Approach 1:
The patent segments the dividing value into separate integer and fractional components, processing them through different path delays. The fractional component is processed through a first path delay while the integer component is processed through a second path delay, preventing their concurrent changes and the resulting artifacts.
Solution Approach 2:
The patent introduces an intermediary mechanism that decouples the changes in integer and fractional components of the dividing value. By using separate path delays and a boundary detection mechanism, the system mediates between the two components to prevent simultaneous transitions that cause spurious energy and noise.
2Reliability
If the PLL uses a feedback loop with a divider to control the multiple relationship between output frequency and reference frequency, then the PLL can generate a stable output frequency, but the system becomes complex when fractional division and frequency modulation are required
Solution Approach 1:
The feedback loop is segmented into multiple path delays with different functions. The first path delay processes the fractional component while the second path delay processes the integer component, allowing the system to maintain stability through structured complexity rather than monolithic design.
Solution Approach 2:
The patent introduces dynamic elements including a dynamically adjustable first path delay and a boundary detection mechanism that actively monitors and responds to N boundary crossings. This dynamic approach allows the system to adapt to changing conditions while maintaining overall stability.
Data Source
AI summary
Techniques are described for implementing fractional dividers in modulated phase-lock loop circuits. For example, a fractional divider can receive a base dividing value having integer and fractional components (e.g., corresponding to a carrier frequency produced by multiplying the dividing value by a reference frequency). The fractional divider can also receive a data signal to modulate the dividing value. Embodiments use a shift value (e.g., preset, or received via a shift input signal) to selectively shift and scale the modulated dividing value to generate a shifted fractional component value. The shifted fractional component value can be added to the base integer component, and de-shifted and de-scaled to generate a corrected dividing value. A feedback signal can then be generated by sequentially dividing a frequency of a clock output signal by the corrected dividing value.