Fractional Frequency Divider Using Clock Gating for Flexible Ratios
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Solution Overview
Problem
Conventional frequency dividers require complex circuit designs and are limited to generating output clock signals with specific frequency ratios, whereas fractional frequency dividers need simpler circuit designs to accommodate various frequency configurations.
Innovation Solution
A fractional frequency divider is designed using a plurality of registers, a counter, a control signal generator, and a clock gating circuit, allowing for the generation of output clock signals with different frequencies by masking or unmasking the input clock signal based on control signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a conventional frequency divider is implemented using flip-flops connected in series, then the circuit structure is simple, but the output frequency is limited to specific ratios (1/2^n) and cannot achieve fractional frequencies
Solution Approach 1:
The frequency division function is segmented into multiple independent stages: an integer frequency divider (first plurality of flip-flops) and a fractional frequency adjustment stage (second plurality of flip-flops with selective coupling). This segmentation allows each stage to perform a specific function while maintaining overall system flexibility without excessive complexity.
Solution Approach 2:
The circuit dynamically configures the coupling between flip-flop stages based on the desired frequency ratio. Control logic selectively enables or disables connections between the integer divider stage and fractional adjustment stage, allowing the system to adapt between integer and fractional division modes without requiring a complete circuit redesign.
2Adaptability or versatility
If a fractional frequency divider is designed to generate output clock signals with special frequencies, then frequency flexibility is improved, but the circuit design becomes complicated
Solution Approach 1:
The frequency divider circuit is designed to perform multiple functions: integer frequency division, fractional frequency division, and programmable frequency ratio selection. By using a unified flip-flop structure that can be configured for different division modes through control signals, the circuit achieves universal functionality without requiring separate dedicated circuits for each mode.
Solution Approach 2:
The circuit changes its operational parameters (division ratio, coupling configuration) based on control inputs. By modifying the state of control flip-flops and the coupling between stages, the same physical circuit can achieve different frequency division ratios, including fractional values, without hardware changes.
3Ease of manufacture
If multiple flip-flops are connected in series for frequency division, then the circuit is easy to implement, but the output frequency is constrained to (1/2^n) ratios
Solution Approach 1:
The fractional frequency adjustment flip-flops are nested within the overall frequency division structure, with their outputs fed back to modulate the input of the integer divider stage. This nested configuration allows the fractional stage to refine the output of the integer stage, achieving fine frequency control while maintaining the simplicity of the basic flip-flop series structure.
Data Source
AI summary
The present invention provides a fractional frequency divider, wherein the fractional frequency divider includes a plurality of registers, a counter, a control signal generator and a clock gating circuit. Regarding the plurality of registers, at least a portion of the registers are set to have values The counter is configured to sequentially generate a plurality of counter values, wherein the plurality of counter values correspond to the at least a portion of the registers, respectively, and the plurality of counter values are generated repeatedly The control signal generator is configured to generate a control signal based on the received counter value and the value of the corresponding register. The clock gating circuit is configured to refer to the control signal to mask or not mask an input clock signal to generate an output clock signal.