Fractional Frequency Divider With Counter-Based Clock Masking
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Solution Overview
Problem
Conventional fractional frequency dividers have complex circuit designs and are limited to generating output clock signals with specific frequencies, making it difficult to achieve simpler configurations for varying frequency requirements.
Innovation Solution
A fractional frequency divider comprising a plurality of registers, a counter, a control signal generator, and a clock gating circuit, which allows for the generation of output clock signals with different frequencies by masking or unmasking the input clock signal based on control signals generated from counter values and register settings, enabling flexible frequency division.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a conventional frequency divider uses multiple flip-flops connected in series, then the output clock frequency can be divided by 2^n (where n is the number of flip-flops), but the frequency division ratio is limited to fixed values and cannot achieve fractional frequencies
Solution Approach 1:
The patent applies dynamics by making the frequency division ratio adjustable and configurable through register settings rather than fixed by hardware configuration. The system dynamically changes the division ratio by loading different values into registers R1-RN, allowing the same circuit to adapt to different frequency division requirements without physical reconfiguration.
Solution Approach 2:
The patent changes the division ratio parameter by controlling the number of enabled clock cycles through register values. By varying the register settings, the system changes the effective division ratio from 1/2 to (N-1)/N, achieving fractional frequency division through parameter adjustment rather than structural modification.
2Adaptability or versatility
If a fractional frequency divider is designed to generate output clock signals with special frequencies, then frequency flexibility is improved, but the circuit design becomes complicated
Solution Approach 1:
The patent achieves universality by designing a single frequency divider circuit that can perform multiple frequency division ratios (1/2, 1/3, 2/3, 1/4, 3/4, etc.) using the same hardware structure. The registers R1-RN serve multiple purposes: controlling clock enabling, storing division ratio parameters, and generating control signals, making the circuit universally applicable to various fractional division requirements.
Solution Approach 2:
The patent segments the frequency division function into N individual clock cycles, each controlled by a corresponding register (R1-RN). This segmentation allows independent control of each clock cycle's enabling state, providing fine-grained control over the output frequency while maintaining a systematic and organized circuit structure.
3Ease of operation
If conventional frequency dividers use fixed flip-flop configurations, then the circuit design is simple, but the output clock frequency cannot be dynamically adjusted
Solution Approach 1:
The patent implements self-service by having the system automatically generate control signals for clock enabling based on the register values. The control signal generator automatically compares counter values with register values and generates the appropriate enable/disable control signals without external intervention, making frequency adjustment automatic once register parameters are set.
Solution Approach 2:
The patent uses feedback through the counter that sequentially generates counter values and feeds them back to the control signal generator. This feedback mechanism allows the system to track the current clock cycle and generate appropriate control signals based on the comparison between counter values and register values, enabling precise frequency control.
Data Source
AI summary
The present invention provides a fractional frequency divider, wherein the fractional frequency divider includes a plurality of registers, a counter, a control signal generator and a clock gating circuit. Regarding the plurality of registers, at least a portion of the registers are set to have values The counter is configured to sequentially generate a plurality of counter values, wherein the plurality of counter values correspond to the at least a portion of the registers, respectively, and the plurality of counter values are generated repeatedly The control signal generator is configured to generate a control signal based on the received counter value and the value of the corresponding register. The clock gating circuit is configured to refer to the control signal to mask or not mask an input clock signal to generate an output clock signal.