Fractional Frequency Divider Requantization With Dithered DTC

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Solution Overview

Problem

Existing fractional frequency dividers suffer from spurious tones due to requantization of accumulated quantization error in the digitally-controllable delay (DCD) controller, which degrades performance in applications like communications, radar, and instrumentation.

Innovation Solution

A fractional frequency divider comprising a multi-modulus divider (MMD) and a digital-to-time converter (DTC) with a dithered requantizer is used to mitigate spurious tones by combining a gain and/or digital predistortion with a dithered requantizer to manage the quantization nonlinearity in the DCD controller.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If requantization is performed in the DCD controller to resolve resolution mismatch between MMD controller and DCD input, then the fractional frequency division can be implemented, but spurious tones are introduced in the output spectrum

Engineering Contradiction:
Improvefractional frequency division capabilityVSAvoidspurious tones
Core Design Contradiction:
Adaptability or versatilityVSObject-generated harmful factors

Solution Approach 1:

A dither signal is introduced as an intermediary element between the accumulated quantization error and the DCD controller input. This dither signal randomizes the quantization error, converting deterministic spurious tones into stochastic noise that can be filtered by the PLL loop, thereby eliminating the harmful spurious tones while preserving fractional frequency division capability

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The quantization error that originally causes spurious tones is converted into a beneficial shaped noise spectrum through the interaction of dithering and the PLL loop filter. The harmful quantization noise is transformed into a form that follows the loop filter's noise transfer function, allowing it to be suppressed in the frequency range of interest

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

2Measurement precision

If the quantization error is accumulated and fed to the DCD controller, then phase alignment can be achieved, but the quantization nonlinearity degrades the output signal quality

Engineering Contradiction:
Improvephase alignment precisionVSAvoidoutput signal quality
Core Design Contradiction:
Measurement precisionVSReliability

Solution Approach 1:

The PLL loop provides feedback that continuously monitors and corrects the phase alignment between reference and divided signals. The loop filter processes the quantization error with feedback, shaping the noise spectrum and suppressing spurious tones, thereby maintaining both phase alignment precision and output signal quality

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The dither signal is applied periodically or continuously to the quantization error before it enters the DCD controller. This periodic dithering action randomizes the quantization error samples, preventing the accumulation of deterministic patterns that would manifest as spurious tones in the output spectrum

Inventive Principle:
Principle #19Periodic action

Data Source

PatentUS20250247099A1Suppressing spurious tones resulting from the requantization of the accumulated quantization error when performing fractional frequency division
Publication Date: 2025.07.31 UNIV COLLEGE DUBLIN NAT UNIV OF IRELAND DUBLIN
  • US20250247099A1 patent drawing
  • US20250247099A1 patent drawing
  • US20250247099A1 patent drawing

AI summary

A fractional frequency divider configured to suppress spurious tones resulting from requantization of an accumulated quantization error has a multi-modulus divider (MMD) and one or more digital-to-time converters (DTCs). Each DTC includes a gain and/or digital predistortion, a dithered requantizer having a multibit input signa, a multibit output signal, and a multibit digitally-controllable delay (DCD). The quantized time delay between the input and output of the DTC is determined by the input from the MMD controller, the gain/digital predistortion and the requantizer. The MMD controller provides an input to the DTC that is proportional to the accumulated time quantization error introduced by the MMD controller, the gain/digital predistortion scales by a gain factor to produce a signal (a[k]) that is combined with a discrete-valued dither signal in the dithered requantizer to provide the control input of the DCD.