Reconfigurable Fractional Divider With Feedback-Stabilized Multiplier
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Solution Overview
Problem
Existing frequency divider circuits in wireless devices often experience unstable output signals due to the lack of feedback loops in multiplier circuits, leading to unwanted variations when used to produce specific frequency divisions, such as 'divide by 1.5', which affects the stability and accuracy of frequency modulation in communication systems.
Innovation Solution
A reconfigurable frequency divider circuit is designed to include a multiplier circuit within a feedback loop, along with a control circuit and adjustable capacitors, to stabilize output signals and enhance the frequency tuning range of frequency synthesizers by incorporating a delay circuit that receives and processes the output signal for phase rotation and stabilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a doubler circuit is used outside the feedback loop of other logical components, then the circuit complexity is reduced, but the output signal stability deteriorates due to unwanted variations
Solution Approach 1:
The patent incorporates the doubler circuit output into the feedback loop of the divide-by-3 circuit. The feedback signal from the divide-by-3 circuit is used to control the doubler circuit, ensuring that variations in the doubler are compensated by the feedback mechanism. This resolves the contradiction by maintaining output stability through feedback while keeping the circuit configuration relatively simple.
2Reliability
If a feedback loop is added to include the doubler circuit, then the output signal stability is improved, but the device complexity increases
Solution Approach 1:
The patent merges the doubler circuit with the existing feedback loop structure of the divide-by-3 circuit. Instead of creating a separate feedback loop for the doubler, the design integrates it into the existing feedback path, allowing the same feedback signal to control multiple stages. This reduces the overall complexity compared to adding entirely separate feedback mechanisms.
3Manufacturing precision
If fixed capacitor values are used in the frequency synthesizer, then the manufacturing precision is improved, but the frequency tuning range is limited
Solution Approach 1:
The patent implements dynamically adjustable capacitor values in the frequency synthesizer. Instead of fixed capacitors, the design uses switchable capacitor arrays or variable capacitors that can be programmed to different values. This allows the same physical circuit to adapt to different frequency requirements while maintaining precise control through digital programming, effectively resolving the contradiction between manufacturing precision and tuning range.
Data Source
AI summary
Aspects of a reconfigurable frequency divider circuit are provided. A reconfigurable frequency divider can include a frequency divider that is configured to receive an input signal. The frequency divider can also include a delay circuit that is configured to receive a divided signal produced by the frequency divider. The frequency divider can also include a frequency multiplier that is configured to produce an output signal based on the delayed signal produced by the delay circuit, wherein the delay circuit is configured to receive the output signal.