Fractional Frequency Divider With Jitter Calibration
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Solution Overview
Problem
Conventional phase locked loop (PLL) cores struggle to meet the requirements of high frequency resolution, low jitter, and scalability for modern electronic devices, particularly in systems on a chip (SoCs) and high-speed data communication systems.
Innovation Solution
The implementation of a fractional divider that includes a coarse programmable divider, a digital to time converter, and a calibration unit, which provides a precise, low-jitter clock output signal by using a fractional divisor and a gain calibration factor to correct for deterministic jitter errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional phase locked loop (PLL) cores are used for clock signal generation, then frequency generation capability is provided, but frequency resolution is insufficient and jitter is high
Solution Approach 1:
The frequency division process is segmented into two independent stages: a coarse programmable divider that handles integer division, and a fine frequency adjustment stage that handles fractional division. This segmentation allows each stage to be optimized independently, achieving both high frequency resolution and low jitter performance without the limitations of conventional single-stage PLL cores.
Solution Approach 2:
A delay-locked loop (DLL) is introduced as an intermediary mechanism between the coarse programmable divider and the final output. The DLL receives the coarse divided signal and applies fine frequency adjustment through programmable delay elements, acting as a mediator that transforms the coarse signal into a precise, low-jitter clock output while maintaining frequency resolution.
2Reliability
If conventional PLL cores are used, then clock signal generation is achieved, but silicon area and power consumption are excessive
Solution Approach 1:
The invention extracts and removes the complex, area-intensive PLL core from the clock generation system. Instead of using a full PLL, the solution extracts only the essential frequency division function and implements it through a simplified architecture combining a coarse programmable divider and a delay-locked loop, dramatically reducing silicon area while maintaining clock signal generation capability.
Solution Approach 2:
The patent replaces the expensive, complex PLL core with simpler, more economical circuit elements. The coarse programmable divider and delay-locked loop use basic digital logic and delay elements that are much less area-intensive than PLL components, achieving the same functional outcome with significantly reduced silicon real estate.
3Reliability
If conventional PLL cores are used, then frequency generation is provided, but scalability and portability are limited
Solution Approach 1:
The system employs dynamically programmable dividers and delay elements that can be reconfigured through control signals. The coarse programmable divider and fine adjustment mechanisms can be programmed to achieve different frequency ratios and output frequencies, providing dynamic adaptability across multiple applications and frequency ranges, enhancing scalability and portability.
Solution Approach 2:
The fractional divider architecture is designed as a universal module that can serve multiple functions: integer frequency division, fractional frequency division, and fine frequency adjustment. This multi-functional design allows the same circuit block to be used across different clock domains and frequency requirements, improving scalability and portability throughout the system.
Data Source
AI summary
Systems and methods provide a fractional signal from a delta sigma modulator to a summer, a combination of an integer value and the fractional signal to a divider, and a divided clock signal from the divider in response to the combination and the input clock signal. The systems and methods also delay the divided clock signal in response to a truncation phase error and gain calibration factor from a calibration unit to provide an output clock signal having equal periods.