Fractional Frequency Divider With Calibration for Low-Jitter Clocks
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Solution Overview
Problem
Conventional phase locked loop (PLL) cores used in modern electronic devices face challenges in achieving high frequency resolution, low jitter, and efficient power consumption, particularly in systems requiring multiple clock domains for diverse functionalities.
Innovation Solution
The implementation of a fractional divider system that includes a coarse programmable divider, a digital-to-time converter, and a calibration unit to provide precise, low-jitter clock signals by using a delta sigma modulator and a calibration engine based on least mean square correlation, allowing for fine ratio-based frequency resolution and scalable, portable solutions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If conventional PLL cores are used to generate clock signals, then frequency generation capability is provided, but silicon area and power consumption increase
Solution Approach 1:
The PLL core is segmented into functional blocks including a frequency synthesizer, divider, and phase detector. This segmentation allows selective activation of components based on operational requirements, reducing overall silicon area while maintaining frequency generation capability through the essential synthesized signal path.
Solution Approach 2:
The frequency synthesizer is designed to generate multiple clock frequencies dynamically, serving multiple clock domains within the system. This multi-functionality eliminates the need for separate dedicated PLL instances for each frequency requirement, thereby reducing total silicon area consumption.
2Use of energy by stationary object
If conventional PLL cores are used to generate clock signals, then frequency generation capability is provided, but power consumption increases
Solution Approach 1:
The PLL system dynamically adjusts its operational state based on detected frequency errors and system requirements. The phase detector and feedback mechanism enable real-time tuning, allowing the system to maintain frequency generation capability while consuming minimal power by activating full functionality only when frequency adjustment is required.
Solution Approach 2:
The PLL core incorporates self-calibration mechanisms where the phase detector automatically detects frequency deviations and triggers corrective adjustments without external intervention. This self-service capability ensures continuous frequency generation reliability while minimizing power consumption by avoiding unnecessary external control signals and manual calibration procedures.
3Measurement precision
If frequency resolution is increased in PLL cores, then frequency precision is improved, but device complexity increases
Solution Approach 1:
A digital-to-time converter is introduced as an intermediary component between the frequency synthesizer and the output stage. This converter translates digital frequency control words into precise time-domain adjustments, achieving high frequency resolution without requiring complex analog filtering and tuning circuits, thereby simplifying the overall device architecture.
Data Source
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AI summary
Systems and methods provide a fractional signal from a delta sigma modulator to a summer, a combination of an integer value and the fractional signal to a divider, and a divided clock signal from the divider in response to the combination and the input clock signal. The systems and methods also delay the divided clock signal in response to a truncation phase error and gain calibration factor from a calibration unit to provide an output clock signal having equal periods.