Fractional Divider Duty-Cycle Regulation for Low Subharmonics
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Solution Overview
Problem
Frequency synthesizers in wireless communication systems face challenges in achieving a wide frequency range with low phase noise and efficient die area usage, as multiple narrow band Voltage-Controlled Oscillators (VCOs) are required, leading to increased cost and complexity due to large inductor and capacitor arrays.
Innovation Solution
Implementing a fractional frequency divider with a regulated duty cycle and balanced subharmonic cancellation, using a frequency division ratio of 1.5 to reduce the number of VCOs needed, and incorporating duty cycle correction circuitry to achieve a 50% duty cycle and minimize subharmonic distortion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple narrow band VCOs are used to provide a wide frequency range, then phase noise performance is improved, but die area increases due to large inductor and capacitor arrays
Solution Approach 1:
A single wideband VCO is designed to cover multiple frequency bands (e.g., 3.8GHz to 4.2GHz and 7.6GHz to 8.4GHz) that would traditionally require separate narrowband VCOs. This universal VCO approach eliminates the need for multiple VCO cores, inductor arrays, and capacitor arrays, significantly reducing die area while maintaining acceptable phase noise performance through fractional division techniques
2Adaptability or versatility
If multiple narrow band VCOs are used to provide a wide frequency range, then frequency coverage is improved, but device complexity increases
Solution Approach 1:
A single wideband VCO replaces multiple narrowband VCOs to provide comprehensive frequency coverage across multiple bands. This reduction in the number of VCO cores and associated control circuits (inductor arrays, capacitor arrays) significantly simplifies the overall device architecture and reduces complexity while maintaining the ability to cover wide frequency ranges through fractional division ratios
Solution Approach 2:
The invention utilizes fractional division ratios (e.g., 1.5x, 2x, 3x, 4x) to expand the effective frequency coverage of a single wideband VCO. By changing the division ratio dynamically, the system can cover multiple frequency bands that would otherwise require separate VCOs, achieving wide frequency coverage with a simpler single-VCO architecture
3Area of stationary object
If a single wideband VCO is used instead of multiple narrow band VCOs, then die area is reduced, but phase noise performance deteriorates
Solution Approach 1:
Fractional division ratios (1.5x, 2x, 3x, 4x) are employed to multiply the output frequency of the wideband VCO, effectively extending the frequency coverage and improving phase noise performance at higher frequencies. The phase noise degradation inherent in frequency multiplication is managed through careful design of the fractional division circuitry and selection of appropriate division ratios for different operating bands
Solution Approach 2:
The system dynamically switches between different fractional division ratios (1.5x, 2x, 3x, 4x) depending on the desired output frequency and band. This dynamic adjustment allows the single wideband VCO to achieve phase noise performance comparable to or better than multiple narrowband VCOs by selecting the optimal division ratio for each operating condition, while maintaining reduced die area
Data Source
AI summary
Systems, devices, and methods related to frequency divider circuitry are provided. An apparatus includes frequency divider circuitry including a first node to receive an input signal; fractional divider circuitry to generate, based on the input signal and a frequency-division ratio, a first signal having a first series of pulses with adjacent pulses triggered by opposite edges of the input signal, wherein the fractional divider circuitry includes first signal selection circuitry; balancer divider circuitry to generate, based on the input signal, a second signal having a second series of pulses aligned to the first series of pulses, wherein the balancer divider circuitry includes second signal selection circuitry triggered by opposite edges of the input signal than the first signal selection circuitry; and a second node to combine the first signal and the second signal.