Fractional Divider Control Using Delta-Sigma Phase Error Cancellation
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Solution Overview
Problem
Existing clock synthesizers with fractional-N dividers have limited frequency coverage and require complex loop filters and VCO control, leading to increased costs and chip area, making them expensive and inflexible.
Innovation Solution
A divider apparatus using a combination of first and second delta sigma modulators to generate divider control signals and fractional signals, which are then used in an interpolator circuit to cancel phase errors, allowing for flexible and efficient frequency division with reduced noise and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a fractional-N divider is used to achieve flexible frequency division, then frequency coverage and flexibility are improved, but device complexity and chip area increase due to complex loop filters and VCO control
Solution Approach 1:
The fractional division operation is segmented into multiple integer division stages. The divider sequentially performs integer divisions with different divisors (e.g., divide by 2 for three periods, then divide by 3 for one period) to achieve the overall fractional division ratio. This segmentation eliminates the need for complex fractional-N divider circuits and loop filters while maintaining frequency flexibility.
Solution Approach 2:
The divider operates in periodic cycles, alternating between different integer division ratios according to a predetermined sequence. For example, it performs divide-by-2 operations for three clock periods followed by a divide-by-3 operation for one clock period, repeating this pattern to achieve an average fractional division ratio. This periodic switching of integer divisors replaces complex continuous fractional control.
2Adaptability or versatility
If a fractional-N divider is used to achieve flexible frequency division, then frequency coverage is improved, but power consumption increases
Solution Approach 1:
The fractional division is broken into sequential integer division stages, each implemented with simple flip-flop based divide-by-2 and divide-by-3 circuits. These segmented integer division operations consume significantly less power than a continuous fractional-N divider would require, while achieving the same frequency synthesis flexibility.
Solution Approach 2:
The invention uses simple, low-cost integer division circuits (flip-flops and basic logic) instead of expensive, complex fractional-N divider hardware. Each division stage is a simple, disposable-like unit that can be quickly switched between different division ratios without requiring complex control infrastructure.
3Device complexity
If integer dividers are used to simplify the circuit, then device complexity is reduced, but frequency coverage is limited
Solution Approach 1:
The divider circuit is designed to perform multiple integer division functions (divide-by-2, divide-by-3, and potentially other divisors) within a single unified structure. By sequentially activating different division stages with different divisors, the circuit achieves universal frequency division capability that far exceeds what a single integer divider could provide, while maintaining relative circuit simplicity.
Data Source
AI summary
A divider control circuit includes a first and a second delta sigma modulator configured to generate a divider control signal for a fractional-N divider and a fractional signal indicative of a phase error in the divider output. The fractional signal is supplied for control of an interpolator circuit. The divider control circuit may be implemented as a look-ahead circuit where two or more divider control signals and fractional signals are generated during a single cycle to allow the divider control circuit to be run at a reduced clock rate.