Fractional-N Frequency Divider Using Phase Selection and Adjustable Delay
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Solution Overview
Problem
Fractional-N frequency dividers have complex circuit designs leading to high power consumption, large chip area, and poor jitter performance.
Innovation Solution
A frequency divider comprising a phase selector and an adjustable delay circuit, which receives clock signals, generates an intermediate signal based on phase characteristics, and further delays this signal to produce a frequency-divided output, reducing circuit complexity and power consumption while improving jitter performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a fractional-N frequency divider is used to generate precise output frequency, then frequency precision is improved, but circuit complexity increases
Solution Approach 1:
The frequency divider is segmented into multiple functional blocks: a phase selector that receives multiple clock signals with different phases and selects one based on control signals, and a delay circuit that delays the selected clock signal by a controllable amount. This segmentation allows the complex fractional-N division function to be achieved through simpler, modular components rather than a monolithic complex circuit.
Solution Approach 2:
The circuit employs dynamic selection of clock phases and delay amounts based on control signals. The phase selector dynamically chooses from multiple clock signals with different phases, and the delay circuit dynamically adjusts the delay amount. This dynamic operation enables fractional-N frequency division while maintaining a relatively simple circuit structure compared to static fractional-N dividers.
2Measurement precision
If a fractional-N frequency divider is used to generate precise output frequency, then frequency precision is improved, but power consumption increases
Solution Approach 1:
By segmenting the frequency divider into a phase selector and a delay circuit, power consumption is reduced as each segment operates independently and can be controlled separately. The phase selector only needs to route signals based on control inputs, and the delay circuit only processes the selected signal, rather than all circuits operating simultaneously as in traditional fractional-N dividers.
Solution Approach 2:
The circuit uses periodic clock signals with different phases that are selectively activated based on the desired division ratio. By periodically selecting and delaying appropriate clock phases, the circuit achieves fractional-N division functionality while keeping power consumption low through selective activation rather than continuous operation of all circuit elements.
3Measurement precision
If a fractional-N frequency divider is used to generate precise output frequency, then frequency precision is improved, but chip area increases
Solution Approach 1:
The segmented architecture with a compact phase selector and delay circuit occupies less chip area compared to the monolithic structure of traditional fractional-N frequency dividers. The phase selector uses minimal logic to route between clock inputs, and the delay circuit uses a compact configurable delay structure, collectively reducing the overall chip footprint while maintaining fractional-N division capability.
4Measurement precision
If a fractional-N frequency divider is used to generate precise output frequency, then frequency precision is improved, but jitter performance worsens
Solution Approach 1:
The dynamic phase selection and delay adjustment allow the circuit to optimize jitter performance by selecting the most appropriate clock phase and delay combination for the current operating conditions. This dynamic adaptation reduces jitter compared to static fractional-N dividers that are locked into fixed configurations, while still achieving the desired frequency precision through the fractional-N division function.
Data Source
AI summary
A frequency divider reduces jitter and power consumption, and includes a phase selector for receiving a plurality of clock signals and outputting an intermediate signal corresponding to phase characteristic of at least one of the clock signals, and an adjustable delay circuit for receiving the intermediate signal and generating an output signal by delaying the received intermediate signal.