Fractional Frequency Divider Phase Delay for Low Jitter RF Clocks
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Solution Overview
Problem
Fractional frequency dividers in wireless communication devices suffer from timing inaccuracy, output jitter, and output spurs due to their design limitations.
Innovation Solution
The proposed solution includes a fractional frequency divider configuration with a counter, multiplexer, and delay module, which incorporates a control unit and selection module to manage clock signals, ensuring accurate phase delay and minimizing jitter and spurs by adjusting the delay units and inverter operation, thereby improving timing accuracy and extending the operating frequency range.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a fractional frequency divider is used to generate various frequency bands, then the power amplifier is protected from harmonic pulling on the voltage-controlled oscillator, but timing inaccuracy occurs
Solution Approach 1:
The frequency divider is divided into multiple parallel paths with different division ratios (first frequency divider with division ratio N1, second frequency divider with division ratio N2). Each path processes the clock signal independently and then combines the outputs through a multiplexer, allowing precise timing control by selecting from multiple pre-calibrated paths.
Solution Approach 2:
The patent changes the division ratio parameter dynamically by switching between different frequency dividers with different ratios (N1 and N2). The multiplexer selects which divider output to use based on the desired frequency band, enabling precise timing adjustment across different operating conditions without compromising the harmonic protection function.
2Reliability
If a fractional frequency divider is used to generate various frequency bands, then the power amplifier is protected from harmonic pulling on the voltage-controlled oscillator, but output jitter occurs
Solution Approach 1:
The system segments the frequency division function into multiple parallel dividers with different ratios. Each divider is optimized for specific frequency ranges, and the multiplexer selects the appropriate divider output to minimize jitter for the current operating frequency, thereby maintaining low output jitter across all frequency bands while preserving harmonic protection.
Solution Approach 2:
The system dynamically switches between different frequency divider paths based on the current operating frequency. The multiplexer control logic adjusts which divider output is selected in real-time, optimizing the division path to minimize jitter for each frequency band while maintaining the protective function against harmonic pulling.
3Reliability
If a fractional frequency divider is used to generate various frequency bands, then the power amplifier is protected from harmonic pulling on the voltage-controlled oscillator, but output spurs occur
Solution Approach 1:
By segmenting the frequency division into multiple paths with different division ratios, the patent distributes the frequency conversion function across multiple specialized dividers. This segmentation allows each divider to operate at optimized frequencies, reducing the generation of spurious signals while maintaining the harmonic protection function through the combined output structure.
Solution Approach 2:
The multiplexer acts as an intermediary that combines the outputs from multiple frequency dividers. It selects and switches between different divider outputs based on the desired frequency band, thereby mediating the signal paths to avoid direct frequency mixing that would generate spurs, while still achieving the frequency conversion and harmonic protection objectives.
4Measurement precision
If multiple delay units and selection modules are added to improve timing accuracy, then timing inaccuracy is minimized, but device complexity increases
Solution Approach 1:
The multiplexer serves multiple functions simultaneously: it selects between different frequency divider paths, implements phase adjustment by choosing from different division ratios, and provides timing optimization. This multi-functionality reduces the need for separate dedicated components for each function, thereby improving timing accuracy without proportionally increasing overall device complexity.
Solution Approach 2:
The patent merges the frequency division function with the phase/timing adjustment function into a unified structure. Multiple frequency dividers with different ratios are combined with a multiplexer that simultaneously performs frequency selection and phase optimization, eliminating the need for separate timing adjustment circuits and reducing overall system complexity while achieving high timing precision.
Data Source
AI summary
The present disclosure relates to a fractional frequency divider, a radio frequency transceiver, and a method of configuring a phase delay in the fractional frequency divider. The fractional frequency divider comprises a counter, a multiplexer, and a delay module. The method is applicable to the fractional frequency divider. The radio frequency transceiver comprises the fractional frequency divider, and the fractional frequency divider adopts the method. According to the aforesaid technical solution, the present disclosure has advantages as follows: the embodiments of the present disclosure can minimize the timing inaccuracy and suppress the output jitter and output spurs; and the embodiments of the present disclosure can effectively extend the operating frequency range of the fractional frequency divider.