Open-Loop Fractional Frequency Divider With Phase Interpolation
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Solution Overview
Problem
Existing frequency dividers require large circuit areas, high costs, and significant power consumption, and those using open loop dividers often produce inaccurate non-integer frequency outputs.
Innovation Solution
An open loop fractional frequency divider comprising an integer divider, a control circuit, and a phase interpolator that generates an output clock using coarse-tune and fine-tune control signals to achieve precise frequency division, with the phase interpolator controlling the contribution of frequency-divided clocks to produce an accurate output clock.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple phase-locked loops are used to generate multiple clocks with different frequencies, then frequency division accuracy is improved, but circuit area increases, cost increases, and power consumption increases
Solution Approach 1:
The patent merges the functions of multiple phase-locked loops into a single phase interpolator that can generate multiple frequency-divided clocks simultaneously. The phase interpolator receives a single reference clock and generates multiple output clocks with different frequencies by controlling the contribution ratios of divided clocks, thereby reducing circuit area while maintaining frequency division accuracy.
Solution Approach 2:
The phase interpolator is designed as a universal circuit that can generate multiple frequency-divided clocks with different frequency ratios from a single reference clock. By adjusting the contribution ratios controlled by coarse-tune and fine-tune signals, the same circuit can produce various frequency divisions without requiring separate phase-locked loops for each frequency.
2Device complexity
If open loop dividers are used to generate multiple frequency-divided clocks, then circuit area is reduced, but frequency division accuracy deteriorates when non-integer frequencies are required
Solution Approach 1:
The patent introduces dynamic control mechanisms (coarse-tune and fine-tune control signals) that allow the phase interpolator to dynamically adjust the contribution ratios of different frequency-divided clocks. This dynamic adjustment capability enables accurate generation of non-integer frequencies by continuously varying the mixing ratios, overcoming the static limitations of traditional open loop dividers.
Solution Approach 2:
The patent changes the control parameters from simple integer division ratios to continuous contribution ratios controlled by multi-bit signals. By varying the contribution ratios of different frequency-divided clocks through coarse-tune and fine-tune signals, the system can achieve precise non-integer frequency divisions that were previously impossible with fixed open loop divider designs.
3Measurement precision
If multiple phase-locked loops are used to achieve accurate frequency division, then frequency division accuracy is improved, but power consumption increases
Solution Approach 1:
The patent combines the functions of multiple power-consuming phase-locked loops into a single phase interpolator circuit. By consolidating the frequency generation function into one circuit that can produce multiple frequency-divided clocks simultaneously, the overall power consumption is significantly reduced while maintaining the ability to generate accurate non-integer frequencies.
Data Source
AI summary
Disclosed is an open loop fractional frequency divider including an integer divider, a control circuit, and a phase interpolator. The integer divider processes an input clock according to the setting of a target frequency to generate a first frequency-divided clock and a second frequency-divided clock. The control circuit generates a coarse-tune control signal and a fine-tune control signal according to the setting. The phase interpolator generates an output clock according to the first frequency-divided clock, the second frequency-divided clock, and the two control signals. The two control signals are used for determining a first current, and their reversed signals are used for determining a second current. The phase interpolator controls a contribution of the first (second) frequency-divided clock to the generation of the output clock according to the first (second) frequency-divided clock, the reversed signal of the first (second) frequency-divided clock, and the first (second) current.