Fractional-N Divider Control With Phase Interpolator for Low-Noise Synthesis
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Solution Overview
Problem
Existing clock synthesizers with integer dividers have limited frequency coverage and require complex loop filters and VCO control, leading to increased costs and chip area, making them expensive for significant portions of the market, while fractional-N dividers introduce noise that is costly to filter.
Innovation Solution
A divider apparatus using a combination of first and second delta sigma modulators to generate control signals for a fractional-N divider, with a phase interpolator circuit to correct phase errors, allowing for flexible and low-cost clock synthesizer design by approximating desired divider ratios and reducing noise through look-ahead techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If integer dividers are used in clock synthesizers, then frequency coverage is limited, but device complexity and cost are reduced
Solution Approach 1:
The patent segments the division operation into integer and fractional components, using separate circuits for each. The integer divider handles the integer portion of the division ratio, while a separate fractional divider handles the fractional portion, allowing independent optimization of each segment.
Solution Approach 2:
The patent employs dynamic switching between different division ratios in the fractional divider based on control signals from a delta-sigma modulator. This allows the system to adaptively change the division ratio to achieve precise frequency synthesis while maintaining flexibility in frequency coverage.
2Adaptability or versatility
If fractional-N dividers are used to expand frequency coverage, then adaptability improves, but noise is introduced that increases device complexity
Solution Approach 1:
The patent extracts the noise-generating fractional division operation from the main signal path and processes it separately through a dedicated fractional divider and delta-sigma modulator. This separation allows the noise to be managed independently through digital filtering in the modulator rather than requiring complex analog noise filtering.
Solution Approach 2:
The patent implements feedback through the delta-sigma modulator that monitors and corrects the fractional division ratio dynamically. The modulator uses feedback to shape the quantization noise spectrum and push it out of the band of interest, reducing the need for complex noise filtering while maintaining frequency coverage.
3Adaptability or versatility
If fractional-N dividers are used to improve frequency coverage, then adaptability increases, but phase error and jitter increase
Solution Approach 1:
The patent introduces a phase interpolator as an intermediary component between the integer and fractional dividers. This phase interpolator combines the outputs of both dividers and corrects phase errors by interpolating between the two signals, thereby maintaining phase accuracy while enabling fractional division for expanded frequency coverage.
Solution Approach 2:
The patent performs preliminary phase correction by the phase interpolator before the corrected signal proceeds to subsequent stages. The interpolator pre-compensates for phase errors introduced by fractional division, ensuring that the phase accuracy is maintained before the signal is used in further processing.
Data Source
AI summary
A divider control circuit includes a first and a second delta sigma modulator configured to generate a divider control signal for a fractional-N divider and a fractional signal indicative of a phase error in the divider output. The fractional signal is supplied for control of an interpolator circuit. The divider control circuit may be implemented as a look-ahead circuit where two or more divider control signals and fractional signals are generated during a single cycle to allow the divider control circuit to be run at a reduced clock rate.