Fractional-N Divider Using Phase Selection for High-Frequency PLLs
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Solution Overview
Problem
Existing fractional-N feedback dividers for Phase-Locked Loops (PLLs) are complex and require a large number of logic circuits, making them difficult to implement efficiently, especially for high-frequency applications.
Innovation Solution
A divider that utilizes a phase selection circuit to switch between phase-separated clock signals from a voltage-controlled oscillator (VCO) to generate a fractional control signal, reducing the complexity and logic circuits required by using high-speed prescalers and programmable counters to achieve divide-by-(N+⅓) or (N+⅔) operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If general methods of implementing fractional-N dividers such as sigma-delta arithmetic divider are used, then fractional feedback division can be achieved, but the implementation becomes complicated and occupies a large number of logic circuits
Solution Approach 1:
The patent segments the feedback division function into multiple parallel integer dividers (first integer feedback divider, second integer feedback divider, third integer feedback divider) that operate simultaneously on different phases of the VCO signal. Each divider handles a specific phase (e.g., 0°, 120°, 240°), and their outputs are combined through logic circuits to achieve the fractional division effect. This segmentation distributes the complexity across multiple simple units rather than requiring one complex fractional divider.
Solution Approach 2:
The patent merges the outputs of multiple parallel integer dividers through combination logic circuits. The select signals from each integer divider are combined using OR gates or similar logic to produce the final divided feedback signal. This merging approach allows the system to achieve fractional-N division functionality by combining multiple integer-N division results, thereby reducing the overall complexity compared to implementing a single complex fractional divider.
2Reliability
If fractional-N feedback dividers are implemented for high frequency PLL applications, then stable clock signals can be generated, but the implementation complexity increases significantly
Solution Approach 1:
The feedback division function is segmented into multiple parallel integer dividers operating on different phases of the VCO signal. Each divider is simpler to implement and can be optimized independently, reducing the overall implementation complexity while maintaining the stability required for high-frequency PLL applications.
Solution Approach 2:
Each parallel divider is configured with specific local characteristics tailored to its phase input, allowing optimization for high-frequency operation. The select signals and combination logic are designed with local quality considerations to ensure proper timing and phase alignment, thereby maintaining system reliability without requiring uniform complex design throughout.
Data Source
AI summary
A divider can include a phase selection circuit that switches between a plurality of phase-separated clock signals in response to a fractional control signal to form a selected clock signal, the selected clock signal being utilized to generate a second clock signal; and a counter that receives the second clock signal and generates the fractional control signal and a transition control signal, the transition control signal indicating when the second clock signal should switch states in response to a transition of the selected clock signal, the counter generating a feed-back clock signal.