Fractional Divider with Phase Shifting for Low-Power PLL Synchronization
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Solution Overview
Problem
The operating speeds of peripheral devices such as memory, communication, and graphic devices have not kept pace with the speed of processors, leading to a speed mismatch, particularly in data transmission where clock signal synchronization is critical, necessitating improved fractional dividers and phase locked loops to enhance synchronization and reduce power consumption and circuit area.
Innovation Solution
A fractional divider comprising an integer divider, delta-sigma modulator, phase shifter, quantization noise canceller, and digital-to-time converter, which generates a final division clock signal by overlapping clock phases and canceling quantization noise, reducing the dynamic range and power consumption of the digital-to-time converter.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a digital-to-time converter (DTC) is used to generate fractional division clock signals, then frequency division accuracy is improved, but power consumption and circuit area increase due to the large dynamic range required
Solution Approach 1:
The patent segments the fractional division process into multiple stages: integer division by N, followed by selective gating of divided clock signals based on fractional control signals. This replaces the need for a single high-resolution DTC with multiple lower-resolution components, reducing power consumption and circuit area while maintaining frequency division accuracy.
Solution Approach 2:
The patent uses dynamic clock gating controlled by fractional control signals to achieve fine frequency adjustment. By dynamically selecting and gating clock signals based on fractional division ratios, the system achieves high precision frequency control without requiring a large dynamic range DTC, thereby reducing power consumption and circuit complexity.
2Measurement precision
If a digital-to-time converter (DTC) is used to generate fractional division clock signals, then frequency division accuracy is improved, but circuit area increases due to the large dynamic range required
Solution Approach 1:
The patent segments the fractional division process into multiple stages: integer division by N, followed by selective gating of divided clock signals based on fractional control signals. This replaces the need for a single high-resolution DTC with multiple lower-resolution components, reducing power consumption and circuit area while maintaining frequency division accuracy.
Solution Approach 2:
The patent merges integer division functionality with fractional control through clock gating. By combining the integer divided clock signals with fractional control logic, the system achieves high precision frequency control without requiring a large dynamic range DTC, thereby reducing circuit area.
3Productivity
If clock signal transmission speed is increased to match processor speeds, then data transmission rate is improved, but synchronization difficulty increases leading to phase misalignment
Solution Approach 1:
The patent employs a phase-locked loop (PLL) with feedback control to maintain synchronization between clock signals and data transmission. The PLL continuously monitors phase alignment and adjusts the fractional division ratio accordingly, ensuring reliable synchronization even at high transmission speeds where phase misalignment would otherwise occur.
Solution Approach 2:
The patent dynamically changes the fractional division ratio parameter to adjust clock signal timing and maintain synchronization. By modifying the division ratio in response to phase detection feedback, the system compensates for timing variations and maintains reliable synchronization at high data transmission rates.
Data Source
AI summary
A fractional divider processing circuitry is to receive one of a plurality of clock signals as an input clock signal, and generate a first division clock signal based on the input clock signal and a first control signal. Phases of the plurality of clock signals partially overlap each other. The processing circuitry generates a delta-sigma modulation signal based on the first division clock signal and a frequency control word, and generates a second division clock signal based on the plurality of clock signals, the first division clock signal and a second control signal. The second control signal corresponds to a quantization noise of the delta-sigma modulation signal. The processing circuitry generates the second control signal and a digital control word based on the quantization noise of the delta-sigma modulator. The processing circuitry generates a final division clock signal based on the second division clock signal and the digital control word.