Fractional Divider Calibration for Low-Noise Wide-Bandwidth PLLs
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Solution Overview
Problem
Traditional Integer-N PLLs face limitations in achieving finer output frequency resolution due to reduced PLL bandwidth and increased power consumption, while Fractional-N PLLs suffer from quantization noise that restricts loop bandwidth.
Innovation Solution
A fractional dividing module with a quantization level of 0.5 is introduced, comprising an output clock generating circuit with a delay unit and a selecting unit, and a control circuit that adjusts the frequency ratio between the input and output clock signals, along with a calibration method to adjust the delay units and reduce quantization noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the reference clock frequency is lowered to achieve finer output frequency resolution in an Integer-N PLL, then the frequency resolution is improved, but the maximum achievable PLL bandwidth is reduced
Solution Approach 1:
The feedback divider is segmented into multiple sub-dividers (first feedback divider and second feedback divider) that operate at different division ratios. This allows the system to achieve fine frequency resolution through the combination of multiple coarser dividers rather than requiring a single high-precision divider operating at low clock frequency, thereby maintaining higher PLL bandwidth.
Solution Approach 2:
The system dynamically switches between different feedback divider configurations and modes (integer mode and fractional mode) based on the desired output frequency and bandwidth requirements. This dynamic adaptation allows the PLL to achieve fine frequency resolution when needed while maintaining high bandwidth when required, resolving the static trade-off between resolution and bandwidth.
2Measurement precision
If the reference clock frequency is lowered to achieve finer output frequency resolution in an Integer-N PLL, then the frequency resolution is improved, but the loop bandwidth must be reduced to 10% of the reference clock frequency
Solution Approach 1:
By segmenting the feedback division function into multiple dividers, the system achieves fine effective frequency resolution without requiring the reference clock to be slowed down. This maintains the reference clock frequency high enough to support wider loop bandwidths while still achieving the desired frequency resolution through the combined division ratios.
Solution Approach 2:
The system changes the operational parameters of the feedback dividers (division ratios, operating modes) dynamically to achieve fine frequency resolution without changing the reference clock frequency. This allows the loop bandwidth to be set independently based on stability constraints rather than being limited by a lowered reference clock frequency.
3Measurement precision
If a delta-sigma modulator is used to control the feedback divider in a Fractional-N PLL to achieve finer frequency resolution, then the frequency resolution is improved, but quantization noise is introduced that limits the loop bandwidth
Solution Approach 1:
The patent extracts and removes the delta-sigma modulator from the feedback path, replacing it with a pure integer feedback divider system. This eliminates the quantization noise generated by the modulator while maintaining fine frequency resolution through the multi-divider architecture. The harmful quantization noise is taken out of the system entirely rather than being shaped and filtered.
Solution Approach 2:
Instead of using a delta-sigma modulator that creates quantization noise which must then be filtered, the patent uses a different approach where multiple integer dividers are combined to achieve fractional-like resolution without generating quantization noise. The potential harm of quantization noise is converted into benefit by using a noise-free method to achieve the same frequency resolution goal.
4Object-generated harmful factors
If the quantization level of the feedback divider is reduced to reduce quantization noise, then the quantization noise is reduced, but the device complexity increases
Solution Approach 1:
The feedback division function is segmented into multiple simpler integer dividers rather than using a single complex fractional divider with fine quantization levels. This segmentation achieves the same or better frequency resolution without requiring high-precision fractional division, thereby reducing the complexity of individual divider components while eliminating quantization noise.
Data Source
AI summary
A fractional dividing module includes an output clock generating circuit, for receiving an input clock signal and generating an output clock signal according to a first control signal, comprising a first delay unit, for delaying the input clock signal to generate a delayed input clock signal; and a selecting unit, for selecting one of the input clock signal and the delayed input clock signal to generate the output clock signal according to the first control signal; and a control circuit, for dividing the output clock signal to generate the first control signal according to a dividing control signal, wherein the dividing control is adjusted to control a frequency ratio between the output clock signal and the input clock signal.