Multi-Element Fractional Divider PLL for Quantization Noise Suppression
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Solution Overview
Problem
Fractional-N phase lock loops (PLLs) face challenges with quantization noise, particularly in wide-band applications, where conventional methods fail to effectively suppress noise across the entire frequency range, leading to significant spurs and reduced performance.
Innovation Solution
A circuit and method utilizing a multi-element fractional divider with dynamic element matching (DEM) and delta-sigma modulation to generate fractional division ratios, ensuring uniform noise suppression by averaging the division ratios across multiple divider circuits, thereby reducing quantization noise by up to 18 dB compared to conventional designs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a single divider dynamically switches between division values N and N+1 is used, then frequency resolution is achieved, but quantization noise increases causing large spurs
Solution Approach 1:
The single divider is segmented into multiple parallel dividers (first set and second set), each performing fractional division with different division ratios. The outputs are combined through selective switching to achieve the desired average division ratio while distributing quantization error across multiple paths, thereby reducing overall quantization noise and spurs.
2Object-generated harmful factors
If loop filters are used to suppress quantization noise, then noise suppression is achieved, but the quantization noise can still dominate in wide-band PLLs
Solution Approach 1:
Multiple dividers are used in parallel to segment the quantization noise generation process. By combining outputs from multiple dividers with different division ratios through selective switching, the quantization noise is distributed and reduced before entering the loop filter, enabling effective wide-band operation without quantization noise domination.
3Object-generated harmful factors
If multiple divider circuits are used with dynamic element matching, then quantization noise is suppressed uniformly across frequency range, but hardware complexity increases
Solution Approach 1:
The divider function is segmented into multiple parallel divider circuits, each handling a portion of the division task. This segmentation enables uniform quantization noise suppression across the frequency range while keeping each individual divider relatively simple.
Solution Approach 2:
Dynamic element matching is implemented through a selector circuit that dynamically switches between different divider outputs based on control signals. This dynamic switching optimizes the combination of divider outputs to achieve uniform noise suppression while adapting to different operating conditions.
Data Source
AI summary
The exemplified technology provides a circuit and clock synthesis technique that suppresses quantization noise in a ΔΣ fractional-N phase-locked loop (PLL) using a fineresolution multi-element fractional divider. The circuit and clock synthesis method beneficially suppresses noise uniformly over the entire frequency range. The circuit can be implemented using mostly digital circuitry, and is applicable for use with both analog and digital PLLs. With an 8-element fractional divider, it is observed that the circuit and clock synthesis technique can suppress quantization noise while incurring only a small increase in hardware complexity.