Fractional Frequency Divider Using Single-Edge CMOS Flip-Flops
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Solution Overview
Problem
Fractional frequency dividers face accuracy degradation and reduced processing time due to non-50% duty cycles and the use of double-edge triggered flip-flops, which increase power consumption and circuit area.
Innovation Solution
Implementing a frequency divider with single-edge triggered flip-flops and eliminating the need for CML-to-CMOS converters by using CMOS components, reducing the critical timing path components and relaxing timing constraints to allow for higher operating frequencies and lower power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If double-edge triggered flip-flops are used to identify half-cycle of input clock, then processing time is reduced by one-half, but power consumption increases and circuit area increases
Solution Approach 1:
The patent divides the frequency division function into multiple single-edge triggered flip-flops that process different phases of the clock signal separately. Instead of using one double-edge triggered flip-flop to handle both rising and falling edges simultaneously, the circuit uses multiple single-edge triggered flip-flops staged in sequence, where each flip-flop processes one edge type. This segmentation reduces power consumption while maintaining the time efficiency benefits.
2Loss of time
If both rising and falling edges of input clock are used to generate flip-flop output signals, then processing time is reduced by one-half, but device complexity increases
Solution Approach 1:
The patent segments the clock edge processing into separate stages using multiple single-edge triggered flip-flops. Each flip-flop is triggered by only one edge type (rising or falling), and they are arranged in a staged configuration where the output of one feeds into the next. This approach maintains the processing time advantage of utilizing both clock edges while reducing circuit complexity compared to using double-edge triggered flip-flops.
Solution Approach 2:
The patent transitions from a single-dimension approach (using both edges simultaneously in one flip-flop) to a multi-dimensional staged approach where different flip-flops operate on different clock edges in sequence. This dimensional change in the processing architecture allows the circuit to achieve the same time efficiency without the complexity of double-edge triggering in a single element.
3Adaptability or versatility
If CML-to-CMOS converters are used in the critical timing path, then signal compatibility is achieved, but timing constraints are tightened and operating frequency is limited
Solution Approach 1:
The patent extracts the CML-to-CMOS conversion function from the critical timing path by using CMOS components throughout the frequency division circuit. Instead of having CML flip-flops followed by converters in the critical path, the entire frequency division is performed using CMOS single-edge triggered flip-flops. This removes the timing-critical conversion step while maintaining signal compatibility through appropriate CMOS design and buffering outside the critical path.
Solution Approach 2:
The patent substitutes the CML (current-mode logic) system with a CMOS (complementary metal-oxide-semiconductor) system for the frequency division function. By replacing CML flip-flops and converters with CMOS flip-flops, the circuit eliminates the need for CML-to-CMOS conversion in the critical timing path, thereby relaxing timing constraints and enabling higher operating frequencies while maintaining the necessary signal compatibility.
4Measurement precision
If duty cycle of input clock is not equal to 50%, then edge transitions are not equally spaced, but using double-edge triggering can compensate for this
Solution Approach 1:
The patent segments the duty cycle compensation function across multiple single-edge triggered flip-flops staged in sequence. Each flip-flop processes one clock edge and contributes to the overall frequency division ratio. By staging multiple single-edge triggered flip-flops rather than using a single double-edge triggered flip-flop, the circuit achieves accurate edge transition alignment for non-50% duty cycle clocks while reducing power consumption.
Data Source
AI summary
A frequency divider circuit (200) includes a frequency sub-divider (201) to provide a frequency divided clock, a delay circuit (250) configured to delay the frequency divided clock by N+0.5 cycles of the input clock to generate a delayed clock, and an output circuit (202) configured to generate an output clock based on the frequency divided clock and the delayed clock, where the output clock has a frequency that is equal to 1/(N+0.5) times a frequency of the input clock, and N is an integer greater than one.