Fractional-N Divider Calibration for Low-Spur Phase Compensation
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Solution Overview
Problem
Fractional N-frequency synthesizers generate undesirable fractional spurs due to periodic switching in division ratios, which phase compensation circuits struggle to mitigate effectively without proper calibration.
Innovation Solution
A system and method for calibrating the phase compensation circuit of a fractional N-frequency divider by generating a jitter-free calibration time window, determining oscillator periods, and calculating calibration control words to adjust the phase compensation circuit and reduce fractional spurious signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If a phase compensation circuit is added to mitigate fractional spurs, then the output signal quality is improved, but the device complexity increases and calibration difficulty arises
Solution Approach 1:
The patent applies preliminary action by performing calibration of the phase compensation circuit before normal operation. A calibration mode is activated that generates calibration patterns and adjusts the phase compensation circuit parameters in advance, so that when normal operation begins, the circuit is already optimized and ready to effectively mitigate fractional spurs without requiring complex real-time adjustments.
Solution Approach 2:
The patent implements self-service through an automatic calibration process that uses internal resources of the frequency synthesizer itself. The calibration mode utilizes the existing VCO, dividers, and phase compensation circuit to generate calibration signals and perform self-adjustment, eliminating the need for external calibration equipment and reducing overall system complexity.
2Object-affected harmful factors
If the phase interpolator is calibrated to mitigate fractional spurs, then the output signal quality is improved, but the calibration process requires additional time and complexity
Solution Approach 1:
The patent applies periodic action by implementing calibration at specific intervals rather than continuously. The calibration mode is activated periodically or at predetermined moments (such as during initialization or at scheduled maintenance intervals), allowing the system to operate normally between calibration events. This reduces the total time spent in calibration while maintaining effective spur mitigation.
Solution Approach 2:
The patent implements skipping by using accelerated calibration procedures that rush through the calibration process when necessary. The calibration mode uses simplified calibration patterns and faster adjustment algorithms that can complete calibration more quickly, sacrificing some precision for speed when time is critical, while still achieving adequate spur mitigation.
3Measurement precision
If the division ratio is periodically changed to achieve fractional frequency, then the frequency resolution is improved, but fractional spurious signals are generated
Solution Approach 1:
The patent applies the intermediary principle by introducing a phase compensation circuit as a mediator between the frequency divider and the output. This circuit receives the divided signals and applies phase adjustments that compensate for the spurious signals generated by periodic division ratio changes. The phase compensation circuit acts as an intermediary element that preserves the frequency resolution benefit while filtering out the harmful fractional spurs.
Solution Approach 2:
The patent implements parameter changes by dynamically adjusting the phase compensation parameters based on the current division ratio and operating conditions. The calibration process establishes optimal phase compensation parameters for different division ratios, and the system switches between pre-calibrated parameter sets as the division ratio changes, maintaining effective spur mitigation across the full frequency range while preserving frequency resolution.
Data Source
AI summary
A fractional N-frequency divider having a reduced fractional spurious output signal, which utilizes a multi-modulus frequency divider and an accumulator to generate a calibration-timing window that is used to calibrate two oscillator circuits and a phase compensation circuit. The calibrated phase compensation circuit is then used to mitigate the fractional spurs in the output signal of the fractional N-frequency divider. The fractional N-frequency divider may be implemented into a fractional N-frequency synthesizer.