Self-Calibrating Fractional Divider Circuits for Spur Suppression
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Fractional-N frequency synthesizers generate unwanted low-frequency spurs due to dual-modulus dividers, making them impractical for many applications unless spur reduction techniques are employed, which can be complex and inefficient.
Innovation Solution
A multi-modulus divider with a phase correction circuit and control circuit that performs self-calibration to generate corrected phase correction signals, reducing jitter and nonlinearity, and a digital noise cancellation mechanism to mitigate deterministic noise in the output signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If fractional-N frequency synthesizers use dual-modulus dividers to achieve fine frequency resolution, then frequency resolution is improved, but unwanted low-frequency spurs are generated
Solution Approach 1:
The patent extracts and removes the harmful spurs from the frequency synthesizer output by using a spur rejection filter that specifically targets and eliminates the unwanted low-frequency spurs generated by the dual-modulus divider, while preserving the desired high-frequency output signal
Solution Approach 2:
The patent implements a feedback mechanism where the output signal is monitored for spurs, and the system dynamically adjusts the divider modulation pattern to minimize spur generation, creating a closed-loop control system that continuously optimizes spur suppression
2Object-generated harmful factors
If conventional spur reduction techniques like sigma-delta noise shaping are applied, then spurs are suppressed, but device complexity increases
Solution Approach 1:
The patent uses a simplified model of the divider output pattern to predict and cancel spurs without implementing complex noise shaping circuits, effectively copying the essential behavior needed for spur cancellation while avoiding the complexity of full sigma-delta modulation
3Device complexity
If integer divider ratios are used in feedback path, then circuit simplicity is maintained, but frequency resolution deteriorates
Solution Approach 1:
The patent dynamically switches between different integer divider ratios (N and N+1) in a controlled pattern to achieve an effective fractional division ratio, allowing the system to maintain simple integer divider circuits while achieving fine frequency resolution through time-varying operation
4Reliability
If phase correction circuits are added to reduce jitter, then output fidelity is improved, but device complexity increases
Solution Approach 1:
The patent combines the phase correction functionality with the existing frequency synthesis circuitry by integrating the phase adjustment mechanism into the feedback path, allowing phase correction to be achieved without adding completely separate circuit blocks
Data Source
AI summary
A fractional divider (FD) includes a multi-modulus divider (MMD), which generates a periodic output signal in response to: (i) a periodic reference signal (REFHF), and (ii) a modulus control signal having a value that sets a frequency division ratio (1/P, 1/(P+1)) to be applied to the periodic reference signal. A phase correction circuit is provided, which generates an FD output signal in response to the periodic MMD output signal and a corrected multi-bit phase correction control (CPCC) signal during an active mode of operation. The phase correction circuit further generates an FD output signal in response to the periodic MMD output signal and a preliminary multi-bit phase correction control (PPCC) signal during a calibration mode of operation. A control circuit is provided, which generates the modulus control signal, the PPCC signal and the CPCC signal during the active mode of operation.