Fractional Divider SSC Clocking With One PLL for Lower EMI Complexity
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Solution Overview
Problem
Conventional electronic systems require multiple phase locked loops and spread spectrum modulation stages to produce multiple spread spectrum clock modulated signals, leading to increased chip area, power consumption, and complexity, as well as noise and interference issues.
Innovation Solution
An electronic device with multiple fractional dividers and a single phase locked loop, where each divider is adjusted by a spread spectrum control logic stage to individually modulate the clock signal according to a specific spread spectrum modulation scheme, reducing the need for multiple phase locked loops and simplifying the circuit design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If multiple phase locked loops and spread spectrum modulation stages are used to produce multiple spread spectrum clock modulated signals, then the required EMI standard compliance is achieved, but chip area, power consumption, and complexity increase substantially
Solution Approach 1:
The patent merges multiple phase locked loops into a single shared phase locked loop that generates a common clock signal. Multiple fractional dividers then process this shared clock signal to produce multiple spread spectrum clock modulated outputs. This consolidation reduces the number of phase locked loops from multiple to one, thereby reducing chip area, power consumption, and circuit complexity while maintaining EMI compliance through spread spectrum modulation.
Solution Approach 2:
The shared phase locked loop serves multiple functions by providing a common clock signal to multiple fractional dividers. Each fractional divider then independently applies its own spread spectrum modulation scheme to generate different modulated clock signals. This multi-functional approach allows one phase locked loop to replace what would traditionally require multiple separate phase locked loops.
2Productivity
If multiple phase locked loops are integrated on the same integrated circuit, then multiple spread spectrum clock modulated signals are produced, but noise and interference between phase locked loops occur
Solution Approach 1:
By merging multiple phase locked loops into a single shared phase locked loop, the patent eliminates the noise and interference that would arise from having multiple separate phase locked loops operating simultaneously on the same integrated circuit. The single phase locked loop generates one clean clock signal that is then distributed to multiple fractional dividers, each applying independent spread spectrum modulation without interfering with others.
3Adaptability or versatility
If individual spread spectrum modulation stages are used for each clock signal, then different modulation schemes can be applied, but power consumption and chip area increase
Solution Approach 1:
The patent merges the clock generation function into a single shared phase locked loop while maintaining individual spread spectrum modulation capability through separate fractional dividers. This approach reduces power consumption by eliminating redundant phase locked loops while preserving the flexibility to apply different modulation schemes through the fractional dividers that process the shared clock signal.
Solution Approach 2:
The patent segments the spread spectrum modulation function into separate fractional dividers that operate independently on the shared clock signal. This segmentation allows each divider to apply its own modulation scheme while sharing the common clock generation resource, thereby reducing overall power consumption while maintaining modulation flexibility.
Data Source
AI summary
The invention relates to an electronic device that includes a plurality of buffers and a phase locked loop. For each buffer a fractional divider is provided which is coupled to receive the output from the phase locked loop and configured to feed a divided output signal to a respective buffer. A spread spectrum clock control logic stage in the spread spectrum clock (SSC) is provided which is configured to individually adjust a value of the division of each fractional divider in order to individually and independently modulate the output signal of each fractional divider according to a spread spectrum modulation scheme.