Fractional Frequency Division Using Delta-Sigma Phase Error Correction
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Solution Overview
Problem
Conventional phase locked loop (PLL) cores used in modern electronic devices face challenges in achieving high frequency resolution, low jitter, and efficient power consumption, particularly in systems requiring multiple clock domains for diverse functionalities.
Innovation Solution
The implementation of a fractional divider system that includes a coarse programmable divider, a digital to time converter, and a calibration unit to provide precise, low-jitter clock signals by using a delta sigma modulator and a calibration engine based on least mean square correlation, allowing for fine ratio-based frequency resolution and scalable, portable solutions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If conventional PLL cores are used to generate clock signals, then frequency generation capability is provided, but silicon area and power consumption increase
Solution Approach 1:
The patent extracts the essential frequency division function from the complex PLL core, implementing a standalone fractional divider that can operate independently. This separates the frequency division functionality from the full PLL architecture, reducing the silicon area and power consumption while maintaining the core clock generation capability needed for the application.
Solution Approach 2:
The patent implements a simplified fractional divider that copies only the essential frequency division functionality from the PLL, using a coarse programmable divider combined with a delta-sigma modulator to achieve fractional division ratios. This copied functionality suffices for the clock domain requirements without the overhead of a complete PLL implementation.
2Reliability
If conventional PLL cores are used to generate clock signals, then clock signal generation is achieved, but jitter performance deteriorates
Solution Approach 1:
The patent incorporates a feedback mechanism through the delta-sigma modulator that continuously monitors and adjusts the division ratio to minimize jitter. The modulator uses feedback from the quantization error to optimize the distribution of division ratios, thereby reducing deterministic jitter in the output clock signal while maintaining fractional division capability.
Solution Approach 2:
The patent dynamically changes the division ratio parameter in a controlled manner using the delta-sigma modulator, which sequences the switching between different integer division ratios. This parameter modulation approach reduces deterministic jitter by distributing the quantization error over time, achieving low jitter performance without requiring a complex PLL architecture.
3Measurement precision
If fractional frequency division is implemented with fine resolution, then frequency resolution improves, but device complexity increases
Solution Approach 1:
The patent segments the frequency division function into two parts: a coarse programmable divider that handles integer division ratios, and a delta-sigma modulator that provides fine fractional resolution by dynamically switching between adjacent integer ratios. This segmentation allows the system to achieve high frequency resolution without implementing a single complex fractional divider, thereby reducing overall device complexity.
Solution Approach 2:
The patent uses a dynamic switching mechanism controlled by the delta-sigma modulator that adjusts the division ratio in real-time based on the desired fractional value. This dynamic approach allows the coarse programmable divider to maintain simple static logic while achieving fine frequency resolution through time-varying operation, reducing the complexity compared to a static high-resolution fractional divider.
Data Source
AI summary
Systems and methods provide a fractional signal from a delta sigma modulator to a summer, a combination of an integer value and the fractional signal to a divider, and a divided clock signal from the divider in response to the combination and the input clock signal. The systems and methods also delay the divided clock signal in response to a truncation phase error and gain calibration factor from a calibration unit to provide an output clock signal having equal periods.