Fractional Delay-Locked Loop Synthesizer for Low-Noise Clock Multiplication
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Solution Overview
Problem
Current frequency synthesizers based on phase-locked loops (PLLs) face challenges in minimizing jitter while consuming high power and silicon die area, while those based on delay-locked loops (DLLs) can only generate output frequencies that are integer multiples of the input reference clock signal, limiting their fractional frequency multiplication capability.
Innovation Solution
A phase-locked loop (PLL) incorporating a phase-to-digital converter and a digitally controlled oscillator with a delay-locked loop, which uses a phase detection circuit, delay chain, and multiplexer to generate a periodic output signal with a frequency that is the product of the input signal frequency and a non-integer fractional number, addressing the limitations of both PLLs and DLLs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a phase-locked loop with high-quality VCO is used to minimize jitter, then phase noise performance is improved, but power consumption and silicon die area increase
Solution Approach 1:
The patent replaces the traditional analog VCO-based PLL with a digitally controlled oscillator (DCO) that uses digital delay elements and a delay-locked loop (DLL) mechanism. This substitution of mechanical/analog components with digital components achieves low phase noise performance while reducing power consumption and die area, as digital circuits are more energy-efficient and compact for this specific function.
Solution Approach 2:
The invention changes the operating parameters by using a DLL-based frequency synthesizer that generates output frequencies as integer or fractional multiples of the reference clock. By adjusting the delay elements in the DLL and using a phase-to-digital converter with a DCO, the system achieves flexible frequency multiplication (including fractional multiples) while maintaining low phase noise, thereby improving power efficiency compared to traditional high-quality VCO approaches.
2Use of energy by moving object
If a delay-locked loop is used to reduce power consumption and die area, then power efficiency is improved, but fractional frequency multiplication capability is limited
Solution Approach 1:
The patent enhances the functionality of the DLL by integrating it with a phase-to-digital converter and a digitally controlled oscillator. This combination allows the system to perform both integer and fractional frequency multiplication, making the power-efficient DLL architecture versatile enough to meet various frequency synthesis requirements that previously would have required more complex or power-hungry circuits.
Solution Approach 2:
The invention introduces dynamic control mechanisms where the phase-to-digital converter dynamically adjusts the DCO based on phase error detection, and the DLL dynamically adjusts delay element values. This dynamic operation enables the system to achieve fractional frequency multiplication capabilities while maintaining the power efficiency of the DLL architecture, as the system adapts its parameters rather than requiring fixed, complex hardware for each frequency ratio.
3Adaptability or versatility
If a traditional PLL is used to achieve flexible frequency output, then frequency adaptability is improved, but jitter and phase noise increase
Solution Approach 1:
The patent substitutes the traditional analog PLL components (VCO, analog phase detector, analog loop filter) with digital equivalents (DCO, phase-to-digital converter, digital loop filter). This digital substitution reduces jitter and phase noise because digital circuits are less susceptible to analog noise and supply voltage variations, while the DCO maintains the frequency flexibility of the original PLL through digital control of delay elements.
4Reliability
If a high-quality VCO is used to minimize jitter, then phase noise performance is improved, but silicon die area increases
Solution Approach 1:
The patent replaces the large-area analog VCO with a compact digital implementation using delay elements and a DLL. The DCO achieves the necessary frequency synthesis and phase control functions using small digital logic components, significantly reducing the silicon die area while maintaining or improving phase noise performance through the digital architecture's inherent noise immunity.
Data Source
AI summary
A phase-locked loop includes a phase-to-digital converter that receives a first periodic input signal at a first input and a first feedback signal at a second input. The phase-to-digital converter generates digital signals. A digitally controlled oscillator includes a delay-locked loop that is responsive to the digital signals. The delay-locked loop generates a periodic output signal having an average frequency that is a product of a frequency of the first periodic input signal multiplied by a non-integer fractional number while a phase of the first periodic input signal is unchanging.