Fractional Delay-Locked Loop for Low-Noise Frequency Synthesis
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Solution Overview
Problem
Current frequency synthesizers based on phase-locked loops (PLLs) face challenges in minimizing jitter while consuming large power and silicon die area, while those based on delay-locked loops (DLLs) can only generate output frequencies that are integer multiples of the input reference clock signal, limiting their fractional frequency capabilities.
Innovation Solution
The development of a delay-locked loop (DLL) configuration that includes phase detection circuitry, voltage-controlled delay circuits, and a frequency multiplier to generate a periodic output signal with a frequency that is a product of the input signal frequency and a fractional non-integer number, allowing for fractional frequency synthesis.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a phase-locked loop (PLL) with a high-quality voltage controlled oscillator (VCO) is used to minimize jitter, then phase noise performance is improved, but power consumption and silicon die area increase significantly
Solution Approach 1:
The patent changes the fundamental operating parameters of the frequency synthesizer by replacing the traditional PLL architecture with a DLL architecture. This involves changing from voltage-controlled oscillation to delay-controlled signal propagation, thereby achieving low phase noise without requiring high-power VCO circuits. The delay elements are controlled by voltage to achieve fractional frequency multiplication while maintaining low power consumption.
2Use of energy by moving object
If a delay-locked loop (DLL) is used to reduce power consumption and silicon die area, then power efficiency is improved, but the ability to generate fractional output frequencies is lost
Solution Approach 1:
The patent introduces dynamic control of delay elements through voltage-controlled delay circuits. By dynamically adjusting the delay amount based on feedback from phase detection, the system can achieve fractional frequency multiplication ratios. The delay amount is modulated to generate the desired fractional output frequency while maintaining the low power consumption advantage of DLL architecture.
Solution Approach 2:
The patent implements a feedback mechanism where phase detection circuitry compares the output frequency with a reference frequency and generates control signals to adjust the delay elements. This closed-loop feedback enables the DLL to lock onto and maintain the correct fractional frequency relationship between input and output, thereby achieving fractional frequency capability that was previously only available in PLL architectures.
3Reliability
If a high-quality voltage controlled oscillator (VCO) is used to minimize jitter, then phase noise performance is improved, but silicon die area increases significantly
Solution Approach 1:
The patent extracts and removes the VCO component from the frequency synthesizer architecture, replacing it with delay elements that do not require the same level of circuit complexity or die area. By taking out the high-power VCO and using simpler delay circuits controlled by voltage, the system achieves comparable or better phase noise performance with significantly reduced silicon die area.
4Reliability
If a delay-locked loop (DLL) is used to provide low noise frequency synthesis, then phase noise performance is improved, but the output frequency is limited to integer multiples of the input reference clock
Solution Approach 1:
The patent makes the delay amount dynamic and controllable, allowing the DLL to achieve non-integer multiplication ratios. By dynamically adjusting the delay through voltage control and feedback mechanisms, the system can generate output frequencies that are fractional multiples of the input reference, thereby expanding the output frequency range while maintaining low phase noise characteristics.
Data Source
AI summary
Phase detection circuitry in a delay-locked loop compares a periodic input signal to a feedback signal. The phase detection circuitry generates a delay signal that controls delays of the delay circuits. Two or more output signals of the delay circuits are transmitted to an input of the phase detection circuitry. The delay-locked loop can be configured so that the period of the periodic input signal divided by a delay of one of the delay circuits equals a non-integer rational number when the phase and frequency of the periodic input signal are constant. A frequency multiplier can be coupled to the delay circuits to generate a periodic output signal. The periodic output signal has an average frequency that is a product of the frequency of the periodic input signal multiplied by a fractional non-integer number when the phase and frequency of the periodic input signal are constant.