Fractional FFE Circuit for SerDes Serial Loopback Testing
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Solution Overview
Problem
High-speed serializer/de-serializer (SerDes) links face challenges in internal serial loopback testing due to increased power consumption, sensitivity to power supply-induced jitter, and bandwidth limitations, leading to bit errors and improper component classification, especially as the speed of the SerDes link increases.
Innovation Solution
A wire-line transceiver employing a fractional feed forward equalizer (FFE) circuit with a simple inverter and transmission gate is used to induce a delay within one symbol time, enhancing the eye opening during serial loopback testing and minimizing Inter Symbol Interference (ISI).
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the number of inverters in the transmit path is increased to perform SLB testing at higher speeds, then the SLB testing capability is improved, but power consumption increases and sensitivity to power supply induced jitter increases
Solution Approach 1:
The patent changes the parameter of delay induction by introducing a fractional FFE circuit that provides adjustable delay (e.g., 0.5 UI, 0.25 UI) to compensate for ISI effects at high speeds, eliminating the need to increase the number of inverters and thereby reducing power consumption while maintaining SLB testing capability
2Speed
If the number of inverters in the transmit path is increased to perform SLB testing at higher speeds, then the SLB testing capability is improved, but the area occupied in the SerDes increases
Solution Approach 1:
The patent uses a fractional FFE circuit with adjustable delay parameters to achieve high-speed SLB testing without increasing the number of inverters, thereby maintaining compact area occupation in the SerDes while enabling testing at higher speeds through parameter optimization rather than component proliferation
3Speed
If the number of inverters in the transmit path is increased to perform SLB testing at higher speeds, then the SLB testing capability is improved, but sensitivity to power supply induced jitter increases
Solution Approach 1:
The patent introduces a fractional FFE circuit that provides precise delay control (e.g., 0.5 UI, 0.25 UI) to compensate for ISI effects, reducing the need for additional inverters and thereby decreasing sensitivity to power supply induced jitter while maintaining high-speed SLB testing capability
4Device complexity
If SLB nets are made bandwidth limited due to routing length and operation speed, then the routing complexity is reduced, but ISI causes bit errors at the receiver end
Solution Approach 1:
The patent introduces a fractional FFE circuit as an intermediary element in the SLB path that compensates for ISI effects caused by bandwidth-limited routing, thereby maintaining simple routing design while preventing bit errors at the receiver end through equalization of the signal
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces ISI, enhances eye opening, and extends bandwidth, making high-speed serial loopback testing more efficient with minimal area overhead and cost, while maintaining flexibility across various conditions.
Implementation Method 1
The fractional FFE circuit is configured to induce a delay of less than one symbol time of data, for enhancing an eye opening from the serial loop back line during the serial loop back test
Data Source
AI summary
A wire-line transceiver is configured to perform a serial loop back test. The wire-line transceiver includes an on-chip transmitter, an on-chip receiver and a fractional feed forward equalizer circuit (fractional FFE circuit) in a serial loop back line path between the on-chip transmitter and the on-chip receiver. The fractional FFE circuit is configured to induce a delay one of less than one symbol time of data, for enhancing an eye opening from the serial loop back line during the serial loop back test, compared to a situation where the fractional FFE circuit is not present or is not used.