Fractional Frequency Generator Using a Circulating Delay Circuit
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional frequency generators for fractional frequency division operations require additional phase generating units, leading to increased power consumption and noise due to the need for higher resolution and circuit complexity, which complicates the generation of frequency signals with different frequencies.
Innovation Solution
A low-power open-loop fractional frequency generator that includes a control unit to generate divisor, phase, and circulation signals, a frequency divider for integer division, a circulating delay circuit to generate phase delay signals, a multiplexer for signal selection, and a retimer to produce the output signal, allowing for continuous phase generation with reduced power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a multiphase frequency generator with high-resolution phase generating units is used to improve the resolution of phase signals, then the frequency division resolution is improved, but the power consumption increases
Solution Approach 1:
The patent employs a circulating delay circuit that periodically circulates a single phase signal through multiple delay units to generate multiple phase signals sequentially. This periodic action allows the system to achieve high-resolution phase signals without continuously operating multiple parallel phase generating units, thereby reducing power consumption while maintaining phase signal resolution.
Solution Approach 2:
The patent creates copies of a single phase signal through the circulating delay circuit, where the original phase signal is delayed and circulated to generate multiple phase copies with different phase shifts. This copying approach eliminates the need for multiple independent phase generating units, reducing power consumption while providing the required phase signal diversity and resolution.
2Measurement precision
If more phase generating units are added to improve phase signal resolution, then the frequency division resolution is improved, but the circuit complexity increases
Solution Approach 1:
The patent merges multiple phase signal generation functions into a single circulating delay circuit. Instead of having separate phase generating units for each phase signal, the system combines them into one circuit that circulates and delays a single phase signal to produce all required phase signals, thereby reducing circuit complexity while maintaining phase signal resolution.
Solution Approach 2:
The circulating delay circuit serves multiple functions simultaneously: it generates multiple phase signals, provides phase shifting, and enables frequency division. This multi-functional design eliminates the need for dedicated phase generating units for each function, reducing overall circuit complexity while achieving high-resolution phase signals.
3Object-generated harmful factors
If the loop bandwidth is reduced or programmable frequency divider resolution is enhanced to inhibit quantization noise, then the output noise is reduced, but the circuit area increases
Solution Approach 1:
The patent extracts the noise generation source by eliminating the sigma-delta modulator and feedback loop from the system. By using an open-loop architecture with a circulating delay circuit, the design removes the quantization noise generation mechanism entirely, avoiding the need for additional circuit area to reduce noise through bandwidth reduction or resolution enhancement.
Solution Approach 2:
The patent uses a simple circulating delay circuit with basic delay units instead of complex feedback loops and high-resolution programmable frequency dividers. This approach accepts the simplicity of the components (analogous to using disposable, simple components) to avoid the need for expensive, area-consuming noise reduction mechanisms while achieving acceptable noise performance.
Data Source
AI summary
A frequency generator, includes a control unit, configured to receive an input signal to generate a divisor signal, a phase signal and a circulation signal; a frequency divider, configured to receive the input signal and perform an integer division to the input signal according to the divisor signal, so as to generate a frequency division signal; a circulating delay circuit, coupled to the frequency divider and configured to perform at least one circulating operation to the frequency division signal, and for each circulating operation, generate at least one phase delay signal; a first multiplexer, coupled to the circulating delay circuit and configured to select one signal from the frequency division signal and the at least one phase delay signal according to the phase signal, so as to generate a multiplexed signal; and a retimer, coupled to the first multiplexer and configured to generate an output signal.