Fractional LO Clock Multiplication to Mitigate Oscillator Pulling
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Power amplifiers integrated on the same die as oscillators in User Equipment experience 'pulling' due to electromagnetic coupling, leading to degraded modulation quality and spectral mask issues, especially in Multiple Input Multiple Output systems.
Innovation Solution
Generating and distributing a non-harmonic local oscillator clock to each transceiver chain, which is then multiplied to synthesize a desired harmonic frequency, reducing undesired spurs, phase noise, and power dissipation by using multi-phase injection locked oscillators and injection locked clock multipliers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If Power Amplifiers are integrated on the same die as oscillators, then cost and form-factor are improved, but pulling occurs due to electromagnetic coupling degrading modulation quality
Solution Approach 1:
The patent segments the local oscillator signal generation into multiple independent fractional LO signals, each generated by separate PLLs. This segmentation isolates the oscillators from each other's pulling effects while maintaining integration on the same die, thus preserving both compact form-factor and modulation quality
Solution Approach 2:
The patent introduces an intermediary signal processing stage that combines multiple fractional LO signals through mixing and summation to produce the final composite LO signal. This intermediary approach allows individual oscillators to operate independently without direct coupling, reducing pulling while maintaining integration
2Productivity
If multiple independently modulated PAs are used in MIMO system, then productivity is improved, but pulling on the oscillator is exacerbated
Solution Approach 1:
The patent assigns separate fractional LO signals from different PLLs to different transmit chains in the MIMO system. This segmentation ensures that each PA operates with its own dedicated oscillator signal, preventing mutual pulling between multiple PAs while maintaining full MIMO functionality
Solution Approach 2:
The patent provides each transmit chain with locally generated fractional LO signals tailored to its specific requirements. This local quality approach allows each PA-oscillator pair to be optimized independently, reducing the cumulative pulling effect across multiple MIMO channels
3Speed
If harmonic multiplication is used to generate desired frequency, then frequency synthesis is achieved, but undesired spurs and phase noise are generated
Solution Approach 1:
The patent extracts only the desired harmonic components from the multiplied fractional LO signals while filtering out undesired spurs and harmonics. This extraction approach maintains the frequency synthesis capability while improving spectral purity by removing harmful byproducts
Solution Approach 2:
The patent adjusts the division ratios and multiplication factors of the fractional LO signals to optimize the frequency synthesis process. By carefully selecting parameters such that desired harmonics align with target frequencies while undesired harmonics fall into stopband regions, the system achieves both accurate frequency synthesis and reduced spurs
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively mitigates pulling, reduces phase noise and spurs, and minimizes power dissipation, improving modulation quality and spectral mask performance across MIMO systems.
Implementation Method 1
Oscillators, such as Digitally Controlled Oscillators (DCO) and Voltage Controlled Oscillators (VCO), may be very sensitive to disturbances from the PA that permeate through the substrate of the die due to electromagnetic coupling
Data Source
AI summary
A radio-frequency integrated circuit (RFIC) configured to generate a synthesized clock includes a phase locked loop (PLL) configured to divide down a clock to a non-harmonic frequency; a plurality of multi-phase injection locked clock multipliers (ILCM) directly connected to a plurality of transceiver chains; wherein the PLL is further configured to distribute a divided down clock to at least one of the plurality of multi-phase ILCMs; wherein the plurality of multiphase ILCMs are configured to select a phase of and multiply the divided down clock to synthesize a desired harmonic frequency of the clock and suppress an undesired harmonic frequency of the clock.