Fractional Frequency-Locked Loop Using Sigma-Delta Division
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Solution Overview
Problem
Frequency synthesis in frequency-locked loops faces challenges in achieving non-integer multiples of input frequencies due to difficulties in fractional division, particularly when using digital circuitry, which results in inaccurate frequency differences and performance issues when the division factor N is small.
Innovation Solution
The implementation of a circuit and method that utilize a word length reduction block and sigma-delta modulator to generate a modulated output from a fractional division factor, combined with an integer component, to accurately control a numerically controlled oscillator, allowing for precise fractional division and improved frequency synthesis by separating the fractional component into integer and fractional parts for accurate frequency control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If digital circuitry is used to implement frequency-locked loop, then cost and die area are reduced, but fractional division accuracy deteriorates
Solution Approach 1:
The patent segments the division factor N into an integer component (floor(N)) and a fractional component (N - floor(N)). The integer component is handled by a standard digital counter, while the fractional component is processed separately through a frequency detector that measures the actual frequency difference. This segmentation allows digital circuitry to achieve accurate fractional division by combining coarse integer counting with precise fractional measurement.
2Measurement precision
If a small division factor N is used, then frequency resolution is improved, but fractional division accuracy deteriorates
Solution Approach 1:
The patent introduces a frequency detector as an intermediary element that measures the actual frequency difference between the input signal and the divided feedback signal. This intermediary measurement allows the system to accurately determine the fractional component of the division factor even when N is small, thereby maintaining both frequency resolution and fractional division reliability.
3Device complexity
If fractional division is implemented in digital circuitry, then device complexity is reduced, but frequency synthesis accuracy deteriorates
Solution Approach 1:
The patent employs a dynamic approach where the frequency detector continuously measures the frequency difference and adjusts the interpretation of the division factor accordingly. This dynamic measurement and adjustment mechanism enables accurate frequency synthesis with fractional N while using relatively simple digital circuitry, as the system adapts to the actual frequency relationships rather than relying on complex pre-calculated fractional dividers.
Data Source
AI summary
A circuit for receiving an input signal having a first frequency and generating an output signal having a second frequency. The circuit comprises a forward branch for receiving the input signal and generating the output signal and a return branch for generating a feedback signal from the output signal. The forward branch comprises a frequency detector for receiving the input signal and the feedback signal and outputting a value based on a ratio of a frequency of the feedback signal to the first frequency; a word length reduction block for receiving a fractional component of a first division factor and generating a modulated output; an adder for forming a sum of an integer component of the first division factor and the modulated output of the word length reduction block; a subtracting element for subtracting the output value of the frequency detector from the sum; and an oscillator controlled by an output from the subtracting element.