Fractional-N Charge Pump Noise Compensation Without an Op-Amp
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Solution Overview
Problem
Existing fractional-N frequency synthesizers face challenges in reducing noise, particularly in fractional-N frequency synthesizers, where deterministic noise and random noise can be significant, and existing solutions either consume extra power or introduce additional noise.
Innovation Solution
A charge pump configuration that includes a digital-to-analog converter, a common-gate amplifier, an integrating capacitor, and a low-impedance active load, which operates without an operational amplifier, ensuring low random and deterministic noise while maintaining power efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If an operational amplifier is used in the charge pump to reduce noise, then noise reduction is improved, but power consumption increases
Solution Approach 1:
The patent removes the operational amplifier from the charge pump circuit, extracting the noise-reducing function to a separate noise compensation circuit that uses a digital-to-analog converter and switching mechanism. This eliminates the power consumption penalty of continuously operating an op-amp while maintaining noise reduction through periodic compensation.
Solution Approach 2:
The noise compensation is implemented through periodic switching actions controlled by logic signals. The digital-to-analog converter and switching network operate periodically to inject compensation currents that cancel deterministic noise, achieving noise reduction without requiring continuous power consumption of an operational amplifier.
2Object-affected harmful factors
If a conventional charge pump is used in fractional-N frequency synthesizer, then deterministic noise is generated due to P-N mismatch, but adding noise compensation circuits increases device complexity
Solution Approach 1:
The patent merges the noise compensation function with the existing charge pump structure by using the same switching network and integrating the digital-to-analog converter within the charge pump block. This combination reduces overall device complexity compared to adding separate noise compensation circuits to a conventional charge pump.
Solution Approach 2:
The switching network in the charge pump serves multiple functions: it controls the charge pump operation and simultaneously implements noise compensation by selectively connecting compensation current sources. This multi-functionality reduces the need for additional dedicated noise compensation components.
3Stability of the object's composition
If P-N mismatch is present in the charge pump, then nonlinearity increases causing noise, but correcting it requires additional components
Solution Approach 1:
The patent introduces a digital-to-analog converter as an intermediary that generates compensation currents based on digitally controlled parameters. This intermediary allows precise control of the compensation mechanism without requiring complex analog circuitry, maintaining linearity while minimizing the number of additional components.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution effectively compensates for noise in fractional-N frequency synthesizers, reducing both random and deterministic noise without the need for an operational amplifier, thereby enhancing power efficiency and reducing circuit nonlinearity-related noise.
Implementation Method 1
an integrating capacitor configured to store a charge in accordance with a first logical signal and release the charge in accordance with a second logical signal
Implementation Method 2
a common-gate amplifier configured to provide a path for charge transfer between a second node and a third node in accordance with a third logical signal
Data Source
AI summary
A charge pump includes a DAC (digital-to-analog converter) configured to draw a first current and a second current from a first node and a second node, respectively, in accordance with a first logical signal, a second logical, and a B-bit control word; a common-gate amplifier configured to provide a path for charge transfer between the second node and a third node in accordance with a third logical signal; an integrating capacitor connected to the second node and configured to be either discharged by the DAC or charged by the common-gate amplifier in accordance with a fourth logical signal; and a low-impedance active load connected to the first node.