Fractional-N Clock Synthesizer for Jitter Attenuation in SerDes
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Solution Overview
Problem
Implementing low-bandwidth PLLs for jitter attenuation and clock holdover in integrated circuits is challenging due to large loop filter components and high intrinsic jitter, leading to jitter accumulation and design complexities in SerDes systems.
Innovation Solution
A digital phase-locked loop with a fractional-N clock synthesizer and jitter attenuator, using a recovered clock signal in a feedback loop for digital phase detection and filtering, which controls the fractional-N modulator to generate a transmit clock with reduced jitter accumulation and increased flexibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If low-bandwidth PLLs are used for jitter attenuation, then jitter accumulation is reduced, but large loop filter components and high intrinsic jitter make implementation difficult in integrated circuits
Solution Approach 1:
The patent replaces the traditional analog loop filter with a digital loop filter implemented in the frequency domain using FFT-based filtering. This substitution of mechanical/analog components with digital processing eliminates the need for large physical components while achieving the same jitter attenuation function.
Solution Approach 2:
The patent transforms the filtering operation from the time domain to the frequency domain by using FFT (Fast Fourier Transform). This parameter change allows for more efficient filtering with reduced computational complexity and eliminates the need for large analog components, directly addressing the implementation difficulties in integrated circuits.
2Reliability
If traditional digital PLL implementations are used, then jitter attenuation is achieved, but design complexity and area requirements increase
Solution Approach 1:
The patent merges the loop filter and clock synthesizer functions into a single integrated unit. By combining these separate blocks into one unified structure with shared resources (such as the FFT processor), the overall circuit area is reduced while maintaining the jitter attenuation capability.
Solution Approach 2:
The patent implements a multi-functional architecture where the FFT processor and other computational resources are shared between different functions including the loop filter, clock synthesizer, and jitter analysis. This universal use of components reduces the total area required compared to dedicated separate implementations.
3Adaptability or versatility
If fractional-N clock synthesizers are used, then frequency flexibility is improved, but jitter accumulation may increase without proper attenuation
Solution Approach 1:
The patent implements a feedback mechanism where the output of the fractional-N clock synthesizer is monitored and fed back through the digital loop filter. This feedback loop detects jitter accumulation and actively compensates for it by adjusting the phase and frequency, thereby maintaining signal quality despite the potential for jitter from fractional division.
Solution Approach 2:
The patent introduces a digital loop filter as an intermediary between the fractional-N clock synthesizer and the output stage. This intermediary component processes the synthesized signal in the frequency domain to remove jitter components before the signal is used, thus mediating between the flexible frequency generation and the requirement for low jitter.
Data Source
AI summary
A circuit, such as, but not limited to, a digital phase-locked loop (PLL) or a transport timing loop, uses a fractional-N modulator and a fractional-N clock synthesizer to generate a clock signal, such as a transmit clock signal, from a reference clock signal. One embodiment uses a recovered clock signal derived from serial received data as a positive input to a feedback loop, and uses the transmit clock signal as a negative input to the feedback loop. After digital phase detection and digital filtering, a filtered error signal s is generated and used to control a modified fraction for control of the fractional-N synthesizer. Disclosed techniques advantageously exhibit jitter attenuation and have relatively little jitter accumulation, which are useful characteristics in telecommunication and data communication network clocking applications. Embodiments can be applied to loop timing, clock regeneration, and transport timing applications, and can be used when clock holdover is desirable.