Fractional-N Synthesizer Lock Detection with Variable Delay Compensation
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Solution Overview
Problem
Existing lock detectors for fractional-N frequency synthesizers are inaccurate due to the variable division ratio, leading to difficulties in detecting a locked output frequency.
Innovation Solution
A lock detector that includes a delay unit for the N-divider output frequency clock based on the output value of a fractional modulator, a lock detection unit for comparing the reference frequency clock with the delayed N-divider clock, a counter to count lock detection signals, and a controller to issue a lock identification signal when a preset count is reached.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a typical lock detector is used in a fractional-N frequency synthesizer, then the device complexity is reduced, but the measurement precision of lock detection becomes inaccurate
Solution Approach 1:
The patent applies dynamics by making the delay time variable rather than fixed. The delay unit adjusts its delay duration based on the output value of the fractional modulator, allowing the lock detector to adapt to changing division ratios in fractional-N frequency synthesizers. This dynamic adjustment enables accurate lock detection despite the variable nature of fractional division ratios.
Solution Approach 2:
The patent changes the delay parameter dynamically based on the fractional modulator output. By adjusting the delay time parameter according to the instantaneous division ratio, the system maintains accurate phase comparison between reference and divided clocks, thereby improving lock detection accuracy without requiring a completely complex new architecture.
2Measurement precision
If the N-divider output frequency clock is not delayed, then the device complexity is reduced, but the lock detection becomes inaccurate due to frequency deviations
Solution Approach 1:
The patent applies preliminary action by pre-calculating and applying the appropriate delay to the N-divider output clock before comparison. The delay unit proactively adjusts the clock phase based on expected fractional modulator output values, ensuring that the clocks are properly aligned for accurate lock detection without adding excessive complexity or detection time.
3Measurement precision
If a fixed delay is used in the N-divider output clock, then the device complexity is reduced, but the lock detection accuracy deteriorates due to variable division ratios
Solution Approach 1:
The patent introduces an intermediary mechanism - the delay unit controlled by the fractional modulator output - that mediates between the variable division ratio and the fixed comparison requirement. This intermediary dynamically adjusts the clock phase to compensate for fractional variations, enabling accurate lock detection without requiring a completely complex rearchitecture of the phase detector.
Data Source
AI summary
Disclosed are an apparatus for lock detection suitable for a fractional-N frequency synthesizer and a method thereof. The lock detector for use in the fractional-N frequency synthesizer includes a delay unit delaying an N-divider output frequency clock based on an output value of a fraction ratio modulator, a lock detection unit outputting a lock detection signal by comparing a reference frequency clock with the N-divider output frequency clock delayed by the delay unit, a counter counting the number of lock detection signals received from the lock detection unit, and a controller issuing a command to output a lock identification signal based on the number of lock detection signals counted by the counter.