Fractional-N Synthesizer Digital Filtering for Phase Noise Reduction
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Solution Overview
Problem
Fractional-N synthesizers face performance degradation due to quantization noise from sigma delta modulators and noise contributions from charge pumps, particularly in low power implementations, along with variations in bandwidth causing noise degradation.
Innovation Solution
A frequency synthesizer design incorporating a phase/frequency detector, charge pump, low pass filter, oscillator circuit, feedback divider, sigma delta modulator, and digital filter, where the digital filter reduces quantization noise and the charge pump's non-linearity is addressed by programming current based on integer dividers, and a loop multiplier increases over sampling rates to minimize noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a fractional-N synthesizer uses a sigma delta modulator to achieve fine frequency resolution and wide loop bandwidth, then frequency resolution and bandwidth are improved, but quantization noise degrades performance
Solution Approach 1:
The patent extracts and removes the harmful quantization noise generated by the sigma delta modulator through a dedicated digital filter. The filter is specifically designed to target and eliminate quantization noise components while preserving the useful frequency synthesis function, thereby resolving the contradiction between achieving fine frequency resolution and suppressing quantization noise degradation
Solution Approach 2:
The patent introduces a digital filter as an intermediary component between the sigma delta modulator and the feedback divider. This intermediary element processes the modulator's output to remove harmful quantization noise before it affects the frequency synthesis performance, allowing the system to maintain both fine frequency resolution and low noise levels
2Productivity
If a fractional-N synthesizer uses a charge pump for frequency synthesis, then frequency synthesis functionality is achieved, but charge pump noise becomes a major phase noise contributor in low power implementations
Solution Approach 1:
The patent extracts and removes charge pump noise through carefully timed gating of the charge pump operation. By controlling the charge pump to operate only during specific phases and using synchronized switching, the design eliminates noise contributions while maintaining the essential frequency synthesis functionality of the charge pump
Solution Approach 2:
The patent employs periodic gating of the charge pump operation synchronized with the reference frequency. The charge pump is activated in periodic bursts rather than continuously, which reduces its noise contribution to the phase noise while still achieving the required frequency synthesis capability through controlled charge transfer cycles
3Object-generated harmful factors
If linearization techniques such as offset PFD or dual PFD are used to address charge pump noise, then charge pump noise is reduced, but reference spur increases and timing accuracy becomes more complex
Solution Approach 1:
The patent implements a self-service approach where the system uses its own reference frequency and existing timing signals to gate and control the charge pump operation. Rather than requiring external or additional complex timing generation circuits, the design leverages the system's inherent timing resources to achieve noise reduction, thereby avoiding increased device complexity while still reducing charge pump noise
Data Source
AI summary
The disclosure provides a frequency synthesizer. It includes a PFD that generates an up signal and a down signal in response to a reference signal and a feedback signal. A charge pump generates a control voltage in response to the up signal and the down signal. A low pass filter generates a filtered voltage in response to the control voltage. An oscillator circuit generates an output signal in response to the filtered voltage. A feedback divider is coupled between the oscillator circuit and the PFD, and divides the output signal by a first integer divider to generate the feedback signal. A sigma delta modulator (SDM) generates a second integer divider in response to the feedback signal, the reference signal, the output signal and the first integer divider. A digital filter is coupled between the SDM and the feedback divider, and filters quantization noise associated with the SDM.