Fractional-N PLL Phase Noise Reduction via Behavioral Modeling
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Solution Overview
Problem
Conventional fractional-N PLL circuits face challenges in efficiently determining and minimizing phase noise sources and reducing spurs, with long development times due to difficulty in identifying noise sources, particularly from random number generators and power supply/substrate coupling.
Innovation Solution
A fractional-N PLL structure is designed with a first circuit on an integrated circuit and a programmable second circuit off the IC, using HDL to generate a machine-executable representation, including a voltage-controlled oscillator, phase detector, charge pump, frequency divider, multiplexers, and random number generators, allowing for phase noise determination and optimization by comparing noise sources and modifying the second circuit to decouple power supply and substrate noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional fractional-N PLL circuit is used, then phase noise and spur performance can be improved through circuit modifications, but development time increases significantly due to long manufacture cycles (three months or more per tape out)
Solution Approach 1:
The patent creates a behavioral model (copy) of the fractional-N PLL circuit that replicates phase noise and spur characteristics without requiring physical fabrication. This model allows performance evaluation and optimization to be completed in software simulation rather than through repeated physical tape-outs, dramatically reducing development time while maintaining accuracy in phase noise and spur assessment
Solution Approach 2:
The patent replaces the physical hardware iteration process (mechanical system involving fabrication and measurement) with a behavioral model simulation system. The model uses mathematical representations to predict phase noise and spur performance, eliminating the need for repeated physical tape-outs and manual measurements, thus substituting mechanical iteration with computational analysis
2Reliability
If circuit modifications are made to reduce phase noise, then phase noise performance improves, but the complexity of identifying noise sources increases due to multiple phase noise sources in the system
Solution Approach 1:
The patent segments the phase noise analysis by creating separate behavioral models for different noise sources (VCO, PLL components, random number generator algorithms). Each noise source can be analyzed independently through its own model, allowing systematic identification and optimization without being overwhelmed by the complexity of the complete system
Solution Approach 2:
The patent introduces a behavioral model as an intermediary between the physical circuit and the phase noise measurement. This model acts as a mediator that translates complex interactions of multiple noise sources into analyzable components, enabling systematic identification of dominant noise sources without direct complex hardware probing
3Reliability
If a random number generator uses MASH algorithm to shape noise to high frequency, then phase noise can be reduced, but the difficulty of detecting and measuring actual noise sources increases due to wide band noise coupling through power supply and substrate
Solution Approach 1:
The patent creates behavioral models that replicate the noise shaping effects of MASH algorithms and the coupling paths through power supply and substrate. These models allow measurement of the actual noise impact without requiring physical probing of the complex coupling paths, making detection and measurement feasible through simulation rather than hardware intrusion
Data Source
AI summary
In one general embodiment, a hardware description language (HDL) design structure is encoded on a machine-readable data storage medium, said HDL design structure comprising elements that when processed in a computer-aided design system generates a machine-executable representation of a fractional-N phased-lock-loop (PLL) structure. The fractional-N PLL structure comprises a first circuit located on an integrated circuit, where the first circuit includes a voltage controlled oscillator for generating a periodic output signal, a phase detector for controlling the voltage controlled oscillator, a charge pump for modifying an input to the voltage controlled oscillator, a frequency divider in a feedback path for modifying a frequency of the output signal, a first multiplexer, and a first random number generator. The fractional-N phased-lock-loop (PLL) structure further comprises a second circuit including a second multiplexer and a second random number generator, wherein the second circuit is a programmable circuit located off the integrated circuit and coupled to the first circuit. A method in a computer-aided design system for generating a functional design model of a fractional-N phased-lock-loop (PLL) structure is provided in one embodiment. A design structure embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit is presented in another embodiment.