Fractional-N Synthesizer with Virtual Divider for Low Phase Noise
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Solution Overview
Problem
Fractional-N frequency synthesizers suffer from excessive phase noise due to elongated pulses caused by dynamically shuffling the divisor value, leading to inaccurate phase changes in the output clock of the voltage-controlled oscillator.
Innovation Solution
A fractional-N frequency synthesizer that generates a virtual feedback clock using a fictitious fractional-N divider, employing a dual modulus divider and a first-order delta-sigma modulator to control the probabilities of divisor values, thereby reducing phase noise and maintaining a zero current output in steady state.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a delta-sigma modulator is used to dynamically shuffle the divisor value to achieve fractional-N division, then the frequency synthesis capability is improved, but the phase noise increases due to elongated UP and DN pulses
Solution Approach 1:
The patent segments the pulse generation process by introducing separate UP and DN pulse generators that operate independently based on the modulator output. This segmentation allows precise control over pulse widths, preventing the elongation that occurs in conventional approaches where pulses are coupled through the divisor shuffling mechanism.
Solution Approach 2:
The patent introduces an intermediary mechanism (the controlled divisor and independent pulse generators) that decouples the relationship between divisor value changes and pulse width variations. This intermediary layer ensures that pulse durations remain determined solely by phase differences, not by the dynamic divisor shuffling process.
2Adaptability or versatility
If the divisor value is dynamically shuffled between N_int and (N_int + 1), then fractional-N division is achieved, but the pulse duration is elongated causing excessive phase changes
Solution Approach 1:
The patent applies preliminary action by pre-defining fixed pulse durations in the UP and DN pulse generators before the divisor shuffling occurs. This ensures that pulse widths are established based on phase comparison results alone, independent of subsequent divisor value changes, thereby preventing pulse elongation.
Solution Approach 2:
The patent implements dynamics by allowing the divisor value to change dynamically while keeping the pulse generation process static and predictable. The divisor switches between N_int and (N_int + 1) based on modulator output, but this dynamic change does not affect the predetermined pulse durations, creating a stable timing reference despite divisor variability.
3Adaptability or versatility
If elongated current pulses are generated from the charge pump, then the divisor shuffling is achieved, but excessive phase changes occur in the VCO output clock
Solution Approach 1:
The patent implements feedback by continuously monitoring phase differences through the phase frequency detector and using this information to generate appropriate UP and DN pulses. This feedback loop ensures that pulse generation is always based on actual phase error conditions, preventing excessive phase changes even when the divisor is dynamically shuffled.
Solution Approach 2:
The patent replaces the mechanical coupling between divisor shuffling and pulse width modulation with an electronic control system. The independent pulse generators use electronic timing circuits to produce fixed-duration pulses based on logic signals, substituting the mechanical relationship that caused pulse elongation with a decoupled electronic control architecture.
Data Source
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AI summary
A circuit, with applications to phase-locked loops and frequency synthesis, where a divider circuit shuffles between dividing the output of a voltage-controlled oscillator by N or N+1, where N is an integer, and where a phase frequency detector provides three logic signals to a charge pump so that one of three values of current may be sourced to a loop filter, with the result that the circuit behaves as a conventional phase-locked loop having a fictitious divider circuit that is capable of dividing the output of the voltage-controlled oscillator by a non-integral value.