Fractional-N Synthesizer Virtual Feedback for Low Phase Noise
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Solution Overview
Problem
Existing fractional-N frequency synthesizers suffer from excessive phase noise due to elongated pulses and current pulses from the charge pump, which cause excessive phase changes to the output clock of the voltage-controlled oscillator, making them inefficient in tracking the reference clock.
Innovation Solution
A circuit that generates a virtual feedback clock as if produced by a fictitious fractional-N divider, using a phase frequency detector, a charge pump, and a loop filter to adjust the frequency and phase of the output clock, with a dual modulus divider and a delta-sigma modulator to dynamically control the divisor values, ensuring the virtual feedback clock is aligned with the reference clock, thereby minimizing phase errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a fractional-N frequency synthesizer uses dynamic divisor shuffling to achieve fractional division, then the frequency synthesis capability is improved, but the phase noise increases due to elongated pulses from the charge pump
Solution Approach 1:
The patent creates a virtual feedback clock that copies the characteristics of what a true fractional-N divider would produce, without actually implementing the complex dynamic divisor shuffling hardware. This virtual copy allows the system to achieve fractional-N frequency synthesis while avoiding the harmful elongated pulses that would otherwise be generated by the charge pump.
Solution Approach 2:
The patent introduces an intermediary virtual feedback clock signal that mediates between the integer-N divider and the phase frequency detector. This intermediary signal allows the system to achieve fractional-N division effects without the harmful side effects, as it represents an idealized feedback signal that wouldn't cause excessive phase changes in the VCO.
2Measurement precision
If the charge pump generates current pulses in response to phase detection signals, then the phase frequency detection function is achieved, but the output clock experiences excessive phase changes
Solution Approach 1:
The virtual feedback clock creates a copy of the ideal fractional-N division output, allowing the phase frequency detector to measure phase differences accurately without the charge pump actually generating the harmful current pulses that would result from processing a true fractional-N feedback signal.
Solution Approach 2:
The system performs preliminary action by generating the virtual feedback clock before the charge pump operation. This pre-computed virtual signal allows the phase detection to be accurate while preventing the harmful effect of excessive phase changes, as the charge pump operates on the virtual signal rather than a true fractional-N signal.
3Object-generated harmful factors
If a virtual feedback clock is generated to simulate fractional-N division, then phase noise is reduced, but the device complexity increases
Solution Approach 1:
Instead of implementing complex fractional-N divider hardware with dynamic divisor shuffling, the patent uses a simpler approach that copies the essential characteristics of the fractional-N output through a virtual feedback clock. This copying approach achieves phase noise reduction while avoiding the complexity of true fractional-N division circuits.
Solution Approach 2:
The patent replaces the mechanical/hardware-based fractional-N divider with a signal-processing-based virtual feedback clock generation. This substitution uses software or logic-based computation to create the virtual signal, which is less complex than implementing actual fractional-N division hardware with dynamic reconfiguration.
Data Source
AI summary
A circuit, with applications to phase-locked loops and frequency synthesis, where a divider circuit shuffles between dividing the output of a voltage-controlled oscillator by N or N+1, where N is an integer, and where a phase frequency detector provides three logic signals to a charge pump so that one of three values of current may be sourced to a loop filter, with the result that the circuit behaves as a conventional phase-locked loop having a fictitious divider circuit that is capable of dividing the output of the voltage-controlled oscillator by a non-integral value.