Fractional-N Synthesizer Virtual Feedback Clock for Low Phase Noise
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing fractional-N frequency synthesizers suffer from excessive phase noise due to elongated pulses and subsequent phase changes caused by dynamically shuffling the divisor value to achieve fractional division, which is not effectively managed by prior art circuits.
Innovation Solution
A circuit that generates a virtual feedback clock as if produced by a fictitious fractional-N divider, using a phase frequency detector, charge pump, loop filter, and dual modulus divider, with a delta-sigma modulator to control the divisor values, ensuring the virtual feedback clock is aligned with the reference clock, thereby minimizing phase noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a delta-sigma modulator is used to dynamically shuffle the divisor value to achieve fractional-N division, then the frequency synthesis capability is improved, but excessive phase noise is generated due to elongated pulses and subsequent phase changes
Solution Approach 1:
The patent creates a virtual feedback clock that copies the timing characteristics of what a true fractional-N divider would produce, without actually implementing the dynamic divisor shuffling. This virtual copy eliminates the harmful pulse elongation while preserving the frequency synthesis capability. The virtual feedback clock is generated by detecting the phase relationship between the reference clock and the actual feedback clock, then using this information to generate a clean clock signal that mimics the desired fractional division behavior.
Solution Approach 2:
The patent introduces a virtual feedback clock as an intermediary between the actual feedback clock and the phase frequency detector. This intermediary signal serves as a mediator that translates the phase information into a clean clock signal without introducing the harmful effects of dynamic divisor shuffling. The virtual feedback clock acts as a buffer that preserves the beneficial frequency synthesis while eliminating the harmful phase noise.
2Measurement precision
If the divisor value is dynamically shuffled between Nint and (Nint+1) to achieve fractional division, then the frequency resolution is improved, but the pulse width is elongated causing excessive phase changes
Solution Approach 1:
Instead of actually shuffling the divisor value which causes pulse elongation, the patent creates a virtual feedback clock that copies the timing characteristics of the desired fractional division. This virtual copy provides the necessary frequency resolution information without the harmful side effect of elongated pulses. The virtual feedback clock is generated based on phase detection between the reference and actual feedback clocks, maintaining precise frequency control with clean, narrow pulses.
3Stability of the object's composition
If a virtual feedback clock is generated to eliminate phase noise, then phase stability is improved, but the circuit complexity increases with additional phase frequency detection
Solution Approach 1:
The patent makes the phase frequency detector serve multiple functions: it detects the phase difference between reference and feedback clocks for frequency synthesis, and simultaneously generates the virtual feedback clock for phase noise elimination. This multi-functionality approach improves phase stability without proportionally increasing circuit complexity, as the same hardware components perform multiple tasks. The charge pump and loop filter also benefit from this dual-purpose detection mechanism.
Data Source
AI summary
A circuit, with applications to phase-locked loops and frequency synthesis, where a divider circuit shuffles between dividing the output of a voltage-controlled oscillator by N or N+1, where N is an integer, and where a phase frequency detector provides three logic signals to a charge pump so that one of three values of current may be sourced to a loop filter, with the result that the circuit behaves as a conventional phase-lockup loop fictitious divider circuit that is capable of dividing the output of the voltage-controlled oscillator by a non-integral value.