Fractional Phase Detector Clock Generation for Low-Jitter Synchronization
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Solution Overview
Problem
Existing clock synthesis methods, such as phase-locked loops, often generate clocks with excessive jitter due to ignoring phase information at most transitions of the input clock, which can fail to meet jitter specifications in clock domains requiring precise synchronization.
Innovation Solution
A circuit that generates output clock signals by adjusting the phase of the output clock at every transition of the input signal, using a high-frequency control clock to track the numerical phase value with an accumulator and a fractional phase detector, filtering phase errors to synchronize the output clock with the input signal, thereby reducing jitter.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a phase-locked loop compares phase at only a fraction of input clock transitions (1/denominator integer), then the device complexity is reduced, but the jitter of the output clock increases excessively
Solution Approach 1:
The patent segments the phase comparison process into multiple independent comparators, each handling a specific transition of the input clock. Instead of a single phase detector sampling at 1/denominator integer rate, multiple phase detectors operate in parallel, each comparing phase at different transitions. This segmentation allows utilization of phase information from all input clock transitions while maintaining manageable complexity through modular architecture.
Solution Approach 2:
The patent implements phase comparison at more transitions than the traditional minimum (1/denominator integer), using partial or excessive phase sampling. By comparing phase at multiple intermediate transitions between the minimum required points, the system obtains additional phase information that can be used to reduce jitter. This excessive phase sampling action provides redundant information that improves reliability without requiring complete redesign of the phase-locked loop architecture.
2Reliability
If phase information is utilized at every transition of the input clock, then the jitter of the output clock is reduced, but the device complexity increases
Solution Approach 1:
The patent merges the outputs of multiple phase detectors that each operate at different input clock transitions. By combining the phase comparison results from multiple detectors into a unified control signal for the voltage-controlled oscillator, the system achieves jitter reduction through comprehensive phase information utilization while avoiding the complexity of completely independent control paths. The merging process integrates multiple partial solutions into a coordinated whole.
Solution Approach 2:
The patent creates a multi-functional phase detection system where the phase detection mechanism serves multiple purposes simultaneously. The same basic phase comparator circuitry is reused across multiple transitions through time-multiplexing or parallel operation, making the phase detection subsystem universally applicable to all input clock transitions. This universality reduces overall complexity compared to having completely separate detection circuits for each transition.
Data Source
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AI summary
Circuits are provided that generate from an input signal one or more output clock signals having reduced skew. The input signal has transitions derived from the transitions of an original clock signal having a frequency that differs from the frequency of the output clock signal. The frequency of the output clock signal is a product from multiplying the frequency for the input signal and an integer ratio. The circuit includes an accumulator, a fractional phase detector, and a loop filter. The accumulator periodically adds a numerical offset value to a numerical phase value. The output clock signal is generated from this numerical phase value. The fractional phase detector generates from the numerical phase value a respective numerical phase error for each of the transitions of the input signal. The loop filter generates the numerical offset value from a filtering of the respective numerical phase errors.