Fractional Phase Detector Clocking for Reduced PLL Jitter
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Solution Overview
Problem
Phase-locked loops often generate clocks with excessive jitter when synthesizing output clocks from input clocks with large denominator integers, as they ignore phase information at most transitions, leading to unsatisfactory synchronization in electronic circuits with asynchronous clock domains.
Innovation Solution
A circuit comprising an accumulator, a fractional phase detector, and a loop filter that adjusts the phase of the output clock signal at every transition of the input signal, using a high-frequency control clock to minimize jitter by periodically updating a numerical phase value and generating output clock signals with frequencies that are integer ratios of the input signal, thereby ensuring more frequent phase adjustments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a phase-locked loop uses a large denominator integer to synthesize output clock frequency, then the frequency ratio precision is improved, but the jitter of the output clock increases
Solution Approach 1:
The patent implements feedback by detecting the phase of the input clock at every transition and using this phase information to control the phase of the output clock. The phase detector continuously monitors and adjusts the output clock phase based on real-time input clock phase measurements, ensuring that phase information is not lost even when using large denominator integers for frequency synthesis.
Solution Approach 2:
The patent replaces the traditional mechanical phase-locked loop mechanism with a digital signal processing approach. Instead of using analog phase detectors and voltage-controlled oscillators, the invention uses digital algorithms to detect phase at every transition and compute the required output clock phase adjustments, thereby reducing jitter while maintaining precise frequency ratios.
2Device complexity
If a phase-locked loop compares phase at only a fraction of input clock transitions, then the circuit complexity is reduced, but the phase information utilization is insufficient
Solution Approach 1:
The patent ensures continuous utilization of phase information by detecting the phase of the input clock at every transition rather than at periodic intervals. This continuous phase detection maintains uninterrupted phase information flow, allowing the system to fully exploit all available phase data for controlling the output clock phase.
Solution Approach 2:
The patent changes the detection parameter from periodic sampling to continuous detection at every transition. By modifying how phase information is captured (from occasional samples to every transition), the system maximizes information utilization without proportionally increasing circuit complexity, as the detection mechanism operates naturally at each edge.
3Speed
If the output clock phase is adjusted only at fraction of input transitions, then the processing speed is reduced, but the synchronization precision deteriorates
Solution Approach 1:
The patent performs preliminary detection of the input clock phase at every transition before generating the corresponding output clock transition. By detecting and storing phase information in advance at each input transition, the system prepares the necessary phase data ahead of time, enabling precise synchronization without delaying the output clock generation.
Data Source
AI summary
Circuits are provided that generate from an input signal one or more output clock signals having reduced skew. The input signal has transitions derived from the transitions of an original clock signal having a frequency that differs from the frequency of the output clock signal. The frequency of the output clock signal is a product from multiplying the frequency for the input signal and an integer ratio. The circuit includes an accumulator, a fractional phase detector, and a loop filter. The accumulator periodically adds a numerical offset value to a numerical phase value. The output clock signal is generated from this numerical phase value. The fractional phase detector generates from the numerical phase value a respective numerical phase error for each of the transitions of the input signal. The loop filter generates the numerical offset value from a filtering of the respective numerical phase errors.