Fractional-Phase Digital PLL for Low-Power Accurate Synchronization
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Solution Overview
Problem
Phase-locked loops (PLLs) in electronic circuits, particularly in portable devices like cellular phones, face challenges in reducing power consumption without compromising performance due to the high power consumption of circuit blocks used to adjust frequency and phase of oscillator signals.
Innovation Solution
A digital phase-locked loop (DPLL) is implemented with circuit blocks designed digitally, utilizing a time-to-digital converter (TDC) to determine fractional phases and a synthesized accumulator to track oscillator cycles, allowing for reduced power consumption by disabling the RF accumulator during operation, thus conserving battery power.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If circuit blocks are implemented with analog circuits to achieve precise frequency and phase adjustment, then synchronization accuracy is improved, but power consumption increases
Solution Approach 1:
The patent replaces analog circuit blocks with digital implementation. Specifically, the phase detector, loop filter, and frequency/phase adjusters are implemented as digital circuits rather than analog circuits. This substitution maintains the functional capability of frequency and phase adjustment while significantly reducing power consumption, as digital circuits can operate at lower voltages and consume less dynamic power compared to their analog counterparts.
Solution Approach 2:
The patent changes the operational parameters of the PLL by using digital representation of phase and frequency. Instead of continuous analog signals, the system uses discrete digital values to represent phase differences and frequency adjustments. This parameter change enables the use of digital processing techniques that are more energy-efficient while maintaining the precision required for synchronization.
2Use of energy by moving object
If digital implementation is used to reduce power consumption and circuit area, then power efficiency is improved, but measurement precision may deteriorate
Solution Approach 1:
The patent segments the phase measurement into two distinct components: integer phase (representing complete cycles) and fractional phase (representing the remaining portion of a cycle). The integer phase is handled by a counter that tracks complete oscillator cycles, while the fractional phase is measured by a time-to-digital converter (TDC) with high resolution. This segmentation allows each component to be optimized independently, maintaining overall precision while reducing power consumption through digital implementation.
Solution Approach 2:
The patent introduces a time-to-digital converter (TDC) as an intermediary component that bridges the analog oscillator output and the digital processing stages. The TDC converts the time difference between oscillator edges with high precision into a digital value representing the fractional phase. This intermediary enables accurate fractional phase measurement in the digital domain without requiring high-speed analog-to-digital conversion, thus maintaining precision while reducing power consumption.
3Measurement precision
If RF accumulator is continuously operated to track oscillator cycles, then phase tracking accuracy is improved, but power consumption increases
Solution Approach 1:
The patent segments the phase tracking function between the RF accumulator and the TDC. The RF accumulator handles only the integer phase by counting complete oscillator cycles, operating at a lower rate. The fractional phase is handled by the TDC, which operates only on the fractional remainder. This segmentation allows the RF accumulator to reduce its operating frequency and power consumption while maintaining accurate phase tracking through the combination of integer and fractional components.
Solution Approach 2:
The patent implements periodic updating of the phase information. The RF accumulator updates the integer phase count at each oscillator cycle, while the TDC updates the fractional phase based on the periodic difference between the oscillator signal and the divided reference signal. This periodic action allows the system to maintain accurate phase tracking information without requiring continuous high-power operation of all components simultaneously.
Data Source
AI summary
In one aspect, a digital PLL (DPLL) operates based on fractional portions of input and output phases. The DPLL accumulates at least one input signal to obtain an input phase. The DPLL determines a fractional portion of an output phase based on a phase difference between an oscillator signal from an oscillator and a reference signal, e.g., using a time-to-digital converter (TDC). The DPLL determines a phase error based on the fractional portion of the input phase and the fractional portion of the output phase. The DPLL then generates a control signal for the oscillator based on the phase error. In another aspect, a DPLL includes a synthesized accumulator that determines a coarse output phase by keeping track of the number of oscillator signal cycles based on the reference signal.