Fractional-N PLL CDR Architecture for Low-Jitter Wireline Links
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Solution Overview
Problem
Conventional clock and data recovery (CDR) devices are inadequate for high data rate wireline communication links, struggling with low-jitter performance and susceptibility to electromagnetic coupling due to limited bandwidth and design complexities.
Innovation Solution
The implementation of a fractional-N phase lock loop (PLL) based CDR architecture, which includes a phase detector, loop filter, and a fractional-N PLL with a charge pump and sigma delta modulator, providing low-jitter performance and immunity to noise, while eliminating the need for phase interpolators and ensuring CDR loop stability through calibration techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional CDR devices are used, then device complexity is reduced, but jitter performance deteriorates and susceptibility to electromagnetic coupling increases
Solution Approach 1:
The patent changes the operating parameters of the PLL by implementing a fractional-N division ratio that dynamically adjusts between integer values (N and N+1) based on sigma-delta modulation. This allows the system to achieve fine frequency resolution and low jitter performance without requiring complex phase interpolators, as the division ratio itself becomes a variable parameter rather than a fixed value.
Solution Approach 2:
The patent replaces complex analog phase interpolator circuits with a digitally controlled fractional-N PLL approach. Instead of using analog signal processing and mechanical-like phase interpolation mechanisms, the invention uses digital logic and modulo arithmetic to achieve phase and frequency control, thereby reducing susceptibility to electromagnetic coupling while maintaining low jitter performance.
2Reliability
If conventional CDR devices with limited bandwidth are used, then device complexity is reduced, but immunity to noise deteriorates
Solution Approach 1:
The patent implements a closed-loop feedback mechanism where the phase detector continuously compares the input signal phase with the VCO output phase, and the loop filter adjusts the VCO frequency based on the phase error. This feedback control system provides high immunity to noise and electromagnetic coupling by actively correcting phase deviations in real-time, achieving superior reliability without requiring excessively complex architecture.
Solution Approach 2:
The patent introduces dynamic behavior through the fractional-N division ratio that switches between N and N+1 based on sigma-delta modulation bits. This dynamic adjustment allows the system to adapt to varying frequency requirements while maintaining phase lock, providing both high noise immunity through the feedback loop and flexibility through the variable division ratio without excessive complexity.
3Measurement precision
If fractional-N PLL with dynamic division ratio is used, then frequency resolution is improved, but device complexity increases
Solution Approach 1:
The patent employs periodic switching of the division ratio between N and N+1 at a high frequency determined by the sigma-delta modulator. This periodic action, when averaged over time, produces an effective fractional division ratio with fine frequency resolution. The periodic modulation approach achieves high precision without requiring complex analog circuitry, as the fine resolution is obtained through time-averaging of discrete integer divisions.
Solution Approach 2:
The patent introduces a sigma-delta modulator as an intermediary component that converts the desired fractional frequency ratio into a sequence of integer division commands. This intermediary translates the complex requirement of fractional division into simple integer switching operations, achieving high frequency resolution while keeping the actual PLL architecture relatively simple by mediating between the digital control interface and the analog VCO.
4Object-affected harmful factors
If phase interpolators are eliminated, then susceptibility to electromagnetic coupling is reduced, but design complexity increases
Solution Approach 1:
The patent replaces analog phase interpolator circuits with a digital fractional-N PLL approach. Instead of using analog signal processing and mechanical-like phase interpolation mechanisms that are susceptible to electromagnetic coupling, the invention uses digital logic and modulo arithmetic to achieve phase and frequency control, thereby reducing susceptibility to electromagnetic coupling while maintaining low jitter performance.
Solution Approach 2:
The patent extracts and removes the phase interpolator component from the CDR architecture entirely. By eliminating this vulnerable analog component, the design reduces susceptibility to electromagnetic coupling. The functionality previously provided by phase interpolators is achieved through the fractional-N division mechanism, which uses digital switching and averaging instead of analog signal mixing.
Data Source
AI summary
The present invention relates to data communication and electrical circuits. More specifically, embodiments of the present invention provide a clock and data recovery (CDR) architecture implementation for high data rate wireline communication links. In an embodiment, a CDR device includes a phase detector, a loop filter, and a fractional-N PLL. The fractional-N PLL generates output clock signal based on output of the loop filter. There are other embodiments as well.