Fractional PLL Charge Pump Linearization for Lower Clock Jitter
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Solution Overview
Problem
Closed-loop oscillator circuits, such as PLLs, face issues with quantization noise due to non-linear charge pump characteristics, leading to increased output clock jitter and reduced noise shaping effectiveness.
Innovation Solution
A clock generation unit comprising an oscillator circuit, frequency divider circuit, phase circuit, charge pump circuit, and filter circuit, which uses an early feedback signal to adjust the frequency control signal and attenuate frequency components, thereby mitigating the non-linearity of the charge pump and reducing jitter.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a charge pump based PLL is used to generate fractional frequency clock signals, then frequency flexibility is improved, but output clock jitter increases due to charge pump non-linearity reducing noise shaping effectiveness
Solution Approach 1:
The patent introduces a feedback mechanism where the output clock signal is fed back through a frequency divider to the phase detector. This closed-loop feedback allows the system to continuously monitor and correct phase errors, compensating for charge pump non-linearity and reducing output clock jitter while maintaining fractional frequency capability
Solution Approach 2:
The patent introduces a digital-to-analog converter (DAC) as an intermediary component between the digital frequency control word and the charge pump. This DAC linearizes the charge pump's operation by providing a more accurate analog current output proportional to the digital input, thereby improving noise shaping effectiveness and reducing jitter
2Measurement precision
If delta-sigma modulation is used for noise shaping, then quantization noise is moved to higher frequencies, but charge pump non-linearity causes noise to fold back into the PLL bandwidth increasing jitter
Solution Approach 1:
The patent changes the operating parameters of the charge pump by introducing linearization techniques. This includes using a DAC with high resolution to accurately convert digital frequency control words to analog currents, and adjusting the charge pump's current sources to provide more linear charging/discharging characteristics. These parameter changes ensure that noise shaped by the delta-sigma modulator remains effectively suppressed and does not fold back into the PLL bandwidth
3Reliability
If multiple control signals are generated to compensate for charge pump non-linearity, then noise shaping is improved, but circuit complexity increases
Solution Approach 1:
The patent merges the frequency division function and the early feedback generation into a single frequency divider circuit. The frequency divider simultaneously divides the output clock frequency and generates the early feedback signal needed for linearization, eliminating the need for separate feedback circuits and reducing overall circuit complexity while maintaining noise shaping effectiveness
Data Source
AI summary
An apparatus includes an oscillator, a frequency divider, a phase circuit, a charge pump, and a filter. The frequency divider may generate an early feedback signal using a clock signal, and may assert a feedback signal a number of periods of the clock signal after asserting the early feedback signal. The phase circuit may generate a charge control signal using a reference clock signal and the feedback signal, and may generate a discharge control signal using the early feedback signal, the reference clock signal, and the feedback signal. The charge pump may charge or discharge a circuit node using the charge control signal and the discharge control signal to generate a frequency control signal. The filter circuit may attenuate at least one frequency component of the frequency control signal. The oscillator circuit may modify a frequency of the clock signal using the frequency control signal.