Fractional-N PLL Reconfiguration for Multi-Rate Clock Accuracy
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Solution Overview
Problem
Existing electronic circuits require multiple reference oscillators to operate multiple transceivers at different line rates, leading to increased costs and resource consumption, and face challenges in meeting diverse data reception requirements with varying accuracy needs.
Innovation Solution
A reconfigurable fractional-N frequency generation system for phase-locked loops (PLLs) using a single reference oscillator, incorporating a programmable sigma-delta modulator, frequency divider, and state machine to dynamically adjust the frequency multiplier and order, enabling fast acquisition and high accuracy clock signal generation for multiple transceivers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple reference oscillators are used to operate multiple transceivers at different line rates, then each transceiver can operate at its required line rate, but the cost and resource consumption increase
Solution Approach 1:
The patent implements a single reference oscillator that serves multiple transceivers through a reconfigurable fractional-N PLL system. The PLL can dynamically adjust its frequency multiplication ratio to generate different clock frequencies for different transceivers, making the reference oscillator universal rather than dedicated to each transceiver. This resolves the contradiction by enabling one oscillator to perform the function of multiple oscillators.
Solution Approach 2:
The patent employs a reconfigurable fractional-N PLL with dynamically adjustable parameters including the frequency multiplication ratio and SDM order. The system can adaptively change its configuration based on the required line rates of different transceivers, enabling a single reference oscillator to dynamically serve multiple transceivers with different frequency requirements, thus reducing the total number of oscillators needed.
2Quantity of substance
If a single reference oscillator is used for multiple transceivers, then resource usage is reduced, but meeting diverse accuracy requirements becomes challenging
Solution Approach 1:
The patent utilizes a reconfigurable fractional-N PLL that can dynamically change its frequency multiplication ratio and SDM order parameters to achieve different output frequencies with appropriate accuracy for each transceiver. By adjusting these parameters, the system maintains high precision clock generation even when using a single reference oscillator, thus resolving the accuracy concern.
Solution Approach 2:
The patent implements a phase-locked loop system with feedback control that continuously monitors and adjusts the output frequency to maintain synchronization with the reference signal. This feedback mechanism ensures that even with a single reference oscillator serving multiple transceivers, each transceiver receives accurately synchronized clock signals meeting its specific accuracy requirements.
3Measurement precision
If fractional-N frequency generation is implemented with reconfigurable SDM, then fast acquisition and high accuracy are achieved, but device complexity increases
Solution Approach 1:
The patent divides the frequency synthesis function into separate modular components: an integer divider, a fractional-N divider, and a reconfigurable SDM. This segmentation allows each component to be optimized independently and simplifies the overall control logic, reducing the complexity burden despite the enhanced functionality for fast acquisition and high accuracy frequency generation.
Data Source
AI summary
In an example, a phase-locked loop (PLL) circuit includes an error detector operable to generate an error signal; an oscillator operable to provide an output signal having an output frequency based on the error signal and a frequency band select signal, the output frequency being a frequency multiplier times a reference frequency; a frequency divider operable to divide the output frequency of the output signal to generate a feedback signal based on a divider control signal; a sigma-delta modulator (SDM) operable to generate the divider control signal based on inputs indicative of an integer value and a fractional value of the frequency multiplier, the SDM responsive to an order select signal operable to select an order of the SDM; and a state machine operable to, in an acquisition state, generate the frequency band select signal and set the order of the SDM.