Fractional PLL Reference Clock Generation Without External VCXO
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Solution Overview
Problem
Legacy SONET, Ethernet, and storage systems operating at lower data rates pose challenges in integrating with emerging 100-Gbit OTN infrastructure, requiring efficient methods to aggregate and multiplex multiple lower data-rate client channels while minimizing space and power usage.
Innovation Solution
Incorporating on-chip fractional phase-locked loop (FPLL) circuits within demultiplexing transponders to generate reference clock signals, eliminating the need for external VCXO circuits and enabling independent frequency adjustments for clock signals, thus reducing costs and board space.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If external VCXO circuits are used to generate reference clock signals, then frequency accuracy is improved, but device complexity and board space increase
Solution Approach 1:
The patent integrates the VCXO circuit functionality directly into the demultiplexing transponder chip, merging previously separate external VCXO circuits with the main transponder device. This integration eliminates the need for external VCXO components while maintaining frequency accuracy requirements, thereby reducing device complexity and board space without sacrificing measurement precision.
Solution Approach 2:
The patent introduces a fractional phase-locked loop (FPLL) circuit as an intermediary component within the transponder to generate the reference clock signals that previously required external VCXO circuits. The FPLL acts as a mediator that produces accurate frequency references through fractional division mechanisms, eliminating the need for external voltage-controlled crystal oscillators while maintaining the required frequency precision.
2Stability of the object's composition
If external VCXO circuits are used to generate reference clock signals, then frequency stability is improved, but area of stationary object increases
Solution Approach 1:
The VCXO circuit is merged into the demultiplexing transponder chip, consolidating what was previously a separate external component into the main device footprint. This integration maintains frequency stability through careful circuit design while eliminating the need for additional external VCXO components, thereby reducing the overall board space occupied by the system.
3Productivity
If multiple lower data-rate client channels are aggregated onto a single wavelength, then bandwidth utilization is improved, but device complexity increases
Solution Approach 1:
The demultiplexing transponder is designed with multi-functional capabilities to handle multiple lower data-rate client channels simultaneously, aggregating them onto a single wavelength. The device performs multiplexing, demultiplexing, and clock signal generation for various protocols (SONET, Ethernet, storage systems) within a single integrated platform, improving bandwidth utilization while managing device complexity through standardized multi-functional architecture.
4Adaptability or versatility
If independent frequency adjustments are enabled for clock signals, then adaptability is improved, but device complexity increases
Solution Approach 1:
The patent implements dynamic frequency adjustment capabilities within the FPLL circuit, allowing the clock signal frequencies to be independently tuned and adapted to different requirements. The fractional division mechanisms enable flexible frequency synthesis that can dynamically adjust to various client channel rates while maintaining phase-locking, providing adaptability through programmable frequency control rather than fixed frequency operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution allows for efficient aggregation and multiplexing of lower data-rate channels into higher data-rate streams within the OTN infrastructure, enhancing bandwidth utilization and reducing space and power requirements.
Implementation Method 1
phase detection circuitry to generate a first control signal based on a phase comparison between first and second periodic signals
Implementation Method 2
An oscillator circuit causes a frequency of a third periodic signal to vary based on the first control signal
Implementation Method 3
A frequency divider circuit divides the frequency of the third periodic signal by a frequency division value to generate a frequency of the second periodic signal
Data Source
AI summary
A phase-locked loop circuit includes phase detection circuitry to generate a first control signal based on a phase comparison between first and second periodic signals. An oscillator circuit causes a frequency of a third periodic signal to vary based on the first control signal. A frequency divider circuit divides the frequency of the third periodic signal by a frequency division value to generate a frequency of the second periodic signal. A delta sigma modulator circuit controls the frequency division value based on second control signals. First storage circuits store the second control signals based on third control signals in response to a fourth periodic signal. A second storage circuit stores an output signal based on a fourth control signal. The fourth periodic signal is generated based on the output signal of the second storage circuit.